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參數(shù)資料
| 型號： | IDT72T51253L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 128K X 18 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 9/55頁 |
| 文件大?。?/td> | 544K |
| 代理商： | IDT72T51253L6BBI |
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IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
Pin No.
RCLK
(T10)
Read Clock
HSTL-LVTTL When enabled by
REN
, the rising edge of RCLK reads data fromthe selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
device to be placed on the
PAE
n bus during direct flag operation. During polled flag operation the
PAE
n
bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The
PAE
and
OV
outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are based on
RCLK. RCLK must be continuous and free-running.
HSTL-LVTTL For the 4Q device the RDADD bus is 5 bits. The RDADD bus is a dual purpose address bus. The first
INPUT
function of RDADD is to select a queue to be read from The least significant 2 bits of the bus, RDADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[4:2] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data
can be placed on to the Qout bus, read fromthe previously selected queue on this RCLK edge). On the
next rising RCLK edge after a read queue select, a data word fromthe previous queue will be placed
onto the outputs, Qout, regardless of the
REN
input. Two RCLK rising edges after read queue select, data
will be placed on to the Qout outputs fromthe newly selected queue, regardless of
REN
due to the first
word fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the
PAE
n bus
during strobed flag mode. The most significant 3 bits, RDADD[4:2] are again used to select 1 of 8
possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[1:0]
are dont care during device selection. The device address present on the RDADD bus will be selected
on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout
bus, read fromthe previously selected queue on this RCLK edge). Please refer to Table 2 for details
on RDADD bus.
HSTL-LVTTL The
REN
input enables read operations froma selected queue based on a rising edge of RCLK. A
INPUT
queue to be read fromcan be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of
REN
. Data froma newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of
REN
due to the FWFT operation. A read enable is not
required to cycle the
PAE
n bus (in polled mode) or to select the device, (in direct mode).
HSTL-LVTTL If serial programmng of the multi-queue device has been selected during master reset, the SCLK input
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that
SENI
is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
HSTL-LVTTL During serial programmng of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT
part (via a rising edge of SCLK), provided the
SENI
input of that device is LOW. If multiple devices are
cascaded, the
SENI
input should be connected to the
SENO
output of the previous device. So when serial
loading of a given device is complete, its
SENO
output goes LOW, allowing the next device in the chain
to be programmed (
SENO
will follow
SENI
of a given device once that device is programmed). The
SENI
input of the master device (or single device), should be controlled by the user.
HSTL-LVTTL This output is used to indicate that serial programmng or default programmng of the multi-queue device
OUTPUT
has been completed.
SENO
follows
SENI
once programmng of a device is complete. Therefore,
SENO
will go LOW after programmng provided
SENI
is LOW, once
SENI
is taken HIGH again,
SENO
will also
go HIGH. When the
SENO
output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programmng of the devices will be used, the
SENO
output
should be connected to the
SENI
input of the next device in the chain. When serial programmng of the
first device is complete,
SENO
will go LOW, thereby taking the
SENI
input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the
SENO
output
essentially follows the
SENI
input. The user should monitor the
SENO
output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
HSTL-LVTTL During serial programmng this pin is loaded with the serial data that will configure the multi-queue devices.
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that
SENI
is LOW. In expansion
RDADD
[4:0]
(RDADD4-P16
RDADD3-P15
RDADD2-P14
RDADD1-M16
RDADD0-M15)
Read Address
Bus
REN
(T11)
Read Enable
SCLK
(N3)
Serial Clock
SENI
(M2)
Serial Input
Enable
SENO
(M1)
Serial Output
Enable
SI
(L1)
Serial In
I/O TYPE
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51253L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51253L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BBI | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L5BB | 功能描述:IC FIFO 65536X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L6-7BB | 功能描述:IC FIFO 65536X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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