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參數(shù)資料
| 型號： | IDT72T54262L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 128K X 20 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54262L5BB |
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31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Test Bypass
register, the Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Test Bypass Register
The register is used to allow test data to flow through the device fromTDI
to TDO. It contains a single stage shift register for a mnimumlength in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
The Boundary-Scan Register
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
The Device Identification Register
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determned through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T54242/72T54252/72T54262, the Part Number field con-
tains the following values:
IDT72T54242/252/262 JTAG Device Identification Register
31(MSB)
Version (4 bits)
0X0
28 27
12 11
1 0(LSB)
Part Number (16-bit) Manufacturer ID (11-bit)
00B3 (hex)
1
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
performthe following:
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex
Value
0000
0001
0002
0003
0004
0007
0008
000F
Instruction
Function
EXTEST
SAMPLE/PRELOAD Select boundary scan register
IDCODE
Selects chip identification register
CLAMP
Fix the output chains to scan chain values
HI-IMPEDANCE
Puts all outputs in high-impedance state
OFFSET READ
Read
PAE
/
PAF
offset register values
OFFSET WRITE
Write
PAE
/
PAF
offset register values
BYPASS
Select bypass register
Private
Several combinations are private (for IDT
internal use). Do not use codes other than
those identified above.
Test external pins
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional
TRST
pin or by otherwise moving to the
Test-Logic-Reset state.
Device
IDT72T54242
IDT72T54252
IDT72T54262
Part#Field
4C5 (hex)
4C6 (hex)
4C7 (hex)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T54262L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T54262L5BBG | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T55248L5BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T55248L6-7BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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