參數(shù)資料
型號： IDT72T54262L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 128K X 20 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 7/56頁
文件大?。?/td> 555K
代理商： IDT72T54262L5BB
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
Symbol
D[39:0]
Name
I/O Type
HSTL-LVTTL These are the data inputs for the device. Data is written into the part via these inputs using the respective
INPUT
write port clocks and enables. In Quad mode, these inputs provide four separate busses to the four
separate FIFOs. D[9:0] is FIFO[0], D[19:10] is FIFO[1], D[29:20] is FIFO[2], D[39:30] is FIFO[3].
In Dual mode, these inputs provide two separate busses to the two separate FIFOs. D[19:0] is FIFO[0],
D[39:20] is FIFO[2]. Any unused inputs should be tied to GND.
HSTL-LVTTL These are the Empty Flags (IDT Standard mode) or Output Ready Flag (FWFT mode) corresponding
OUTPUT
(1)
to each of the four FIFOs on the read port. If Dual mode is selected
EF
1/
OR
1 and
EF
3/
OR
3 are
not used and can be left floating.
HSTL-LVTTL These are the echo clock outputs corresponding to each of the four FIFOs on the read port. The
OUTPUT
(1)
echo read clock is guaranteed to transition after the slowest output data switching. If Dual mode is
selected ERCLK1 and ERCLK3 are not used and can be left floating
HSTL-LVTTL These are the echo read enable outputs corresponding to each of the four FIFOs on the read port.
OUTPUT
(1)
The echo read enable is synchronous to the RCLK input and is active when a read operation has
occurred and a new word has been placed onto the data output bus. If Dual mode is selected
EREN
1
and
EREN
3 are not used and can be left floating.
Full Flags 0/1/2/3 or HSTL-LVTTL These are the Full Flags (IDT Standard mode) and Input Ready Flags (FWFT mode) corresponding
Input Ready Flags
OUTPUT
(1)
to each of the four FIFOs on the read port. If Dual mode is selected
FF
1/
IR
1 and
FF
3/
IR
3 are not
0/1/2/3
used and can be left floating.
Flag Select
HSTL-LVTTL Flag select default offset pins. During master reset, the FSEL pins are used to select one of four default
INPUT
PAE
and
PAF
offsets. Both the
PAE
and the
PAF
offsets are programmed to the same value. Values
are: 00 = 7; 01 = 63; 10 = 127; 11 = 1023. The offset value selected is supplied to all internal FIFOs.
First Word Fall
HSTL-LVTTL During Master Reset, FWFT=1 selects First Word Fall Through mode, FWFT=0 selects IDT Standard
Through/ Serial
INPUT
mode. After Master Reset this pin is used for the Serial Data input for the programmng of the
PAE
and
Input
PAF
flag's offset registers.
I/O Select
CMOS
(2)
This input determnes whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL
INPUT
pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be
set to HSTL. If IOSEL is LOW then LVTTL is selected. This signal must be tied to either V
CC
or GND
for proper operation.
Input Width
CMOS
(2)
If Dual mode is selected , this pin is used during master reset to select the input word width bus size
INPUT
for the device. 0 = x10; 1 = x20. If Quad mode is selected the input word width will be x10 regardless
of IW. IW must be tied to V
CC
or GND and cannot be left floating.
Mode
CMOS
(2)
This mode selection pin is used during master reset to select either Quad or Dual mode operation.
INPUT
A HIGH on this pin selects Quad mode, a LOW selects Dual mode.
Master Reset
HSTL-LVTTL This input provides a full device reset. All set-up pins are latched based on a master reset operation.
INPUT
Read and write pointers will be reset to the first location memory. All flag offsets are cleared and
reset to default values determned by FSEL[1:0].
Output Enable
HSTL-LVTTL These are the output enables corresponding to each individual FIFO on the read port. All data outputs
0/1/2/3
INPUT
will be placed into High Impedance if this pin is High. These inputs are asynchronous. If Dual mode
is selected
OE
1 and
OE
3 are not used and should be tied to V
CC
.
Output Width
CMOS
(2)
If Dual mode is selected, this pin is used during master reset to select the output word width bus size
INPUT
for the device. 0 = x10; 1 = x20. If Quad mode is selected the output word width will be x10 regardless
of OW. OW must be tied to V
CC
or GND and cannot be left floating.
Programmable
HSTL-LVTTL These are the programmable almost empty flags that can be used as an early indicator for the empty
Almost-Empty
OUTPUT
(1)
boundary of each FIFO. The
PAE
flags can be set to one of four default offsets determned by the
Flags 0/1/2/3
state of FSEL0 and FSEL1 during master reset. The
PAE
offset value can also be written and read
fromserially by either the JTAG port or the serial programmng pins (SCLK, SI, SDO,
SWEN
,
SREN
).
This flag can operate in synchronous or asynchronous mode depending on the sate of the PFMpin
during master reset. If Dual mode is selected
PAE
1 and
PAE
3 are not used and can be left floating.
Programmable
HSTL-LVTTL These are the programmable almost full flags that can be used as an early indicator for the full
Almost-Full Flags
OUTPUT
(1)
boundary of each FIFO. The
PAF
flags can be set to one of four default offsets determned by the
0/1/2/3
state of FSEL0 and FSEL1 during master reset. The
PAF
offset value can also be written and read
fromserially by either the JTAG port or the serial programmng pins (SCLK, SI, SDO,
SWEN
,
SREN
).
Description
Data Input Bus
EF
0/1/2/3,
OR
0/1/2/3
Empty Flag 0/1/2/3
or Output Ready
Flags 0/1/2/3
ERCLK0/1/2/3 Echo Read Clock
0/1/2/3
EREN
0/1/2/3
Echo Read Enable
0/1/2/3
FF
0/1/2/3,
IR
0/1/2/3
FSEL
[1:0]
FWFT/SI
IOSEL
IW
MD
MRS
OE
0/1/2/3
OW
PAE
0/1/2/3
PAF
0/1/2/3
PIN DESCRIPTIONS
相關(guān)PDF資料
PDF描述
IDT72T54262L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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IDT72T55248L5BB 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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