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| 型號： | IDT72T54262L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 128K X 20 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 50/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54262L5BB |
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50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR)
NOTE:
1. The timng diagramshown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when
RCS0 and
OE
0 are both active, LOW, that is the bus is not in High-
Impedance state.
3.
OE
0 is LOW.
Cycle:
a&b.
At this point the FIFO is empty,
OR
0 is HIGH.
RCS
0 and
REN
0 are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register,
OR
0 goes active, LOW.
RCS
0 is HIGH, therefore the Qn outputs are High-Impedance.
EREN
0 goes LOW to indicate that a new word has been placed on the output register.
d.
EREN
0 goes HIGH, no new word has been placed on the output register on this cycle.
e.
No Operation.
f.
RCS
0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE:
In FWFT mode is important to take
RCS
0 active LOW at least one cycle ahead of
REN
0, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g.
REN
0 goes active LOW, this reads out the second word, Wn+2.
EREN
0 goes active LOW to indicate a new word has been placed into the output register.
h.
Word Wn+3 is read out,
EREN
0 remains active, LOW indicating a new word has been read out.
NOTE:
Wn+3 is the last word in the FIFO.
i.
This is the next enabled read after the last word, Wn+3 has been read out.
OR
0 flag goes HIGH and
EREN0
goes HIGH to indicate that there is no new word available.
4.
OE
0 is LOW, WDDR = LOW, and RDDR = LOW.
Q[9:0]
O/P
Reg.
t
A
t
REF
OR
0
6158 drw32
t
RCSLZ
REN
0
t
ENS
t
ENH
RCS
0
t
ENS
RCLK0
a
b
c
d
e
f
g
h
i
W
n+1
WCLK0
WEN
0
D[9:0]
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK0
EREN
0
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
t
A
W
n
Last Word
t
A
t
A
t
DH
t
DH
t
DH
t
DS
t
DS
1
2
t
ERCLK
HIGH-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T54262L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
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| IDT72T54262L5BBG | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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| IDT72T55248L6-7BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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