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參數(shù)資料
| 型號(hào)： | IDT72V3611L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 64X36 15NS 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問(wèn)時(shí)間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3611L15PF8 |
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3
IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
Symbol
Name
I/O
Description
A0-A35
Port-AData
I/O
36-bitbidirectionaldataportforsideA.
AE
Almost-EmptyFlag
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
in the FIFO is less than or equal to the value in the offset register, X.
AF
Almost-FullFlag
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Offset register, X.
B0-B35
Port-BData.
I/O
36-bitbidirectionaldataportforsideB.
CLKA
Port-A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port-A and can be
asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
Port-BClock
I
CLKB is a continuous clock that synchronizes all data transfers through port-B and can be
asynchronous or coincident to CLKA. EF and AE are synchronized totheLOW-to-HIGH
transitionofCLKB.
CSA
Port-AChipSelect
I
CSAmust be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
The A0-A35 outputs are in the high-impedance state when CSAis HIGH.
CSB
Port-BChipSelect
I
CSBmust be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
The B0-B35 outputs are in the high-impedance state when CSBis HIGH.
EF
EmptyFlag
O
EFis synchronized to the LOW-to-HIGH transition of CLKB. When EFis LOW, the FIFO is empty,
and reads from its memory are disabled. Data can be read from the FIFO to its output register
when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGHtransitionofCLKBafterdataisloadedintoemptyFIFOmemory.
ENA
Port-AEnable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB
Port-BEnable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FF
Full Flag
O
FFis synchronized to the LOW-to-HIGH transition of CLKA. When FFis LOW, the FIFO is full, and
writes to its memory are disabled. FFis forced LOW when the device is reset and is set HIGH by
thesecondLOW-to-HIGHtransitionofCLKAafterreset.
FS1, FS0
Flag-OffsetSelects
I
The LOW-to-HIGH transition of RSTlatches the values of FS0 and FS1, which loads one of four
presetvaluesintotheAlmost-FullandAlmost-EmptyOffsetregister(X).
MBA
Port-AMailboxSelect
I
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
MBB
Port-BMailboxSelect
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects the FIFO output register data for output.
MBF1
Mail1RegisterFlag
O
MBF1is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1is set LOW. MBF1is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the
device is reset.
MBF2
Mail2RegisterFlag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the
device is reset.
ODD/
Odd/EvenParity
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
EVEN
Select
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA
Port-A Parity Error
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
Flag
[Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced
HIGHregardlessofthestateofA0-A35inputs.
PIN DESCRIPTION
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| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PQF | 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L20PF | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L20PF8 | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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