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參數(shù)資料
| 型號： | IDT72V3611L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 64X36 15NS 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3611L15PF8 |
10
IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag register.
Synchronized
Number of Words
to CLKB
to CLKA
in the FIFO
EF
AE
AF
FF
0L
L
H
1 to X
H
L
H
(X+1) to [64-(X+1)]
H
(64-X) to 63
H
L
H
64
H
L
thereadsetstheFFHIGHanddatacanbewritteninthefollowingclockcycle.
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycle
ofareadif theclocktransitionoccursat timetSKEW1orgreateraftertheread.
Otherwise,thesubsequentclockcyclecanbethefirstsynchronizationcycle(see
Figure 6).
ALMOST-EMPTY FLAG ( AE)
The FIFO Almost-Empty flag is synchronized to the port clock that reads
datafromitsarray(CLKB). ThestatemachinethatcontrolstheAEflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythevalueoftheAlmost-FullandAlmost-Empty
Offsetregister(X). Thisregisterisloadedwithoneoffourpresetvaluesduring
a device reset (see the Reset section). The AE flag is LOW when the FIFO
containsXorlesswordsinmemoryandisHIGHwhentheFIFOcontains(X+1)
or more words.
Two LOW-to-HIGH transitions on the port-B clock (CLKB) are required
after a FIFO write for the AE flag to reflect the new level of fill. Therefore, the
AE flag of a FIFO containing (X+1) or more words remains LOW if two CLKB
cycleshavenotelapsedsincethewritethatfilledthememorytothe(X+1)level.
TheAEflagissetHIGHbythesecondCLKBLOW-to-HIGHtransitionafterthe
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition on
CLKBbeginsthefirstsynchronizationcycleifitoccursattimetSKEW2orgreater
afterthewritethatfillstheFIFOto(X+1)words. Otherwise,thesubsequentCLKB
cycle can be the first synchronization cycle (see Figure 7).
ALMOST-FULL FLAG ( AF )
The FIFO Almost-Full flag is synchronized to the port clock that writes
datatoitsarray(CLKA). ThestatemachinethatcontrolsanAFflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate
isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see
theResetsection). TheAFflagisLOWwhentheFIFOcontains(64-X)ormore
wordsinmemoryandisHIGHwhentheFIFOcontains[64-(X+1)]orlesswords.
Two LOW-to-HIGH transitions on the port-A clock (CLKA) are required
after a FIFO read for the AF flag to reflect the new level of fill. Therefore, the
AFflagofaFIFOcontaining[64-(X+1)]orlesswordsremainsLOWiftwoCLKA
cycles have not elapsed since the read that reduced the number of words in
memoryto[64-(X+1)]. TheAFflagissetHIGHbythesecondCLKALOW-to-
HIGHtransitionaftertheFIFOreadthatreducesthenumberofwordsinmemory
to[64-(X+1)]. ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchroni-
zationcycleifitoccursattimetSKEW2orgreaterafterthereadthatreducesthe
numberofwordsinmemoryto[64-(X+1)]. Otherwise,thesubsequentCLKA
cycle can be the first synchronization cycle (see Figure 8).
MAILBOX REGISTERS
Two36-bitbypassregistersareontheIDT72V3611topasscommandand
controlinformationbetweenportAandportB. TheMailboxselect(MBA,MBB)
inputs choose between a mail register and a FIFO for a port data transfer
operation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35datatothemail1
registerwhenport-AwriteisselectedbyCSA,W/RA,andENAwithMBAHIGH.
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register
whenport-BwriteisselectedbyCSB,W/RB,andENBwithMBBHIGH. Writing
data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
AttemptedwritestoamailregisterareignoredwhileitsmailflagisLOW.
When the port-B data (B0-B35) outputs are active, the data on the bus
comesfromtheFIFOoutputregisterwhentheport-BMailboxselect(MBB)input
SYNCHRONIZED FIFO FLAGS
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages.
This is done to improve the flags’ reliability by reducing the probability of
metastableeventsontheiroutputswhenCLKAandCLKBoperateasynchro-
nouslytooneanother. FFandAFaresynchronizedtoCLKA. EFandAEare
synchronizedtoCLKB. Table4showstherelationshipoftheflagstothelevel
ofFIFOfill.
EMPTY FLAG ( EF )
The FIFO Empty Flag is synchronized to the port clock that reads data from
itsarray(CLKB). WhentheEFisHIGH,newdatacanbereadtotheFIFOoutput
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an EF monitors a write
pointer and read pointer comparator that indicates when the FIFO memory
statusisempty,empty+1,orempty+2. AwordwrittentotheFIFOcanberead
totheFIFOoutputregisterinaminimumofthreeport-Bclock(CLKB)cycles.
Therefore, an EF is LOW if a word in memory is the next data to be sent to the
FIFOoutputregisterandtwoCLKBcycleshavenotelapsedsincethetimethe
wordwaswritten. TheEFoftheFIFOissetHIGHbythesecondLOW-to-HIGH
transition of CLKB, and the new data word can be read to the FIFO output
registerinthefollowingcycle.
A LOW-to-HIGH transition on CLKB begins the first synchronized cycle of
a write if the clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 5).
FULL FLAG ( FF )
The FIFO Full Flag is synchronized to the port clock that writes data to its
array(CLKA). WhentheFFisHIGH,aFIFOmemorylocationisfreetoreceive
new data. No memory locations are free when the FF is LOW and attempted
writes to the FIFO are ignored.
EachtimeawordiswrittentotheFIFO,itswritepointerisincremented. The
state machine that controls the FF monitors a write pointer and read pointer
comparatorthatindicateswhentheFIFOmemorystatusisfull,full-1,orfull-2.
From the time a word is read from the FIFO, its previous memory location is
readytobewritteninaminimumofthreeport-Aclockcycles. Therefore,a FF
isLOWiflessthantwoCLKAcycleshaveelapsedsincethenextmemorywrite
location has been read. The second LOW-to-HIGH transition on CLKA after
TABLE 4 – FIFO FLAG OPERATION
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| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PQF | 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L20PF | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L20PF8 | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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