IDT72V3611 3.3V, CMOS SyncFIFOTM 64 x 36 COMMERCIALTEMPERATURERANGE PIN DESCRIPTION (CONTINUED) Symbol" />
參數(shù)資料
型號(hào)： IDT72V3611L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 14/19頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SYNC 64X36 15NS 120-TQFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 同步
存儲(chǔ)容量： 2.3K（64 x 36）
數(shù)據(jù)速率： 67MHz
訪問時(shí)間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V3611L15PF8
4
IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
PEFB
Port-B Parity Error
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
Flag
(Port B) B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity
trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced
HIGH regardlessofthestateoftheB0-B35inputs
PGA
Port-AParity
I
Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity
Generation
generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8,
A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit
of each byte.
PGB
Port-BParity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
Generation
is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17,
B18-B26, and B27-B35. The generated parity bitsareoutputinthemostsignificantbitof
each byte.
RST
Reset
I
Toresetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsof
CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the
EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1
andFS0inputstoselectAlmost-FullandAlmost-Emptyflagoffset.
W/RA
Port-AWrite/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a
Select
LOW-to-HIGHtransitionofCLKA. TheA0-A35outputsareinthehigh-impedancestate
when W/RA is HIGH.
W/RB
Port-BWrite/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a
Select
LOW-to-HIGHtransitionofCLKB. TheB0-B35outputsareinthehigh-impedancestate
when W/RB is HIGH.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V3611L15PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP
IDT72V3611L15PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP
IDT72V3611L15PQF 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V3611L20PF 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V3611L20PF8 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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