IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2 COMMERCIALTEMPERATURERANGE Symbol Name I/O Description " />
參數(shù)資料
型號(hào)： IDT72V3612L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 18/24頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 64X36X2 15NS 120QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 異步
存儲(chǔ)容量： 4.6K（64 x 36 x2）
數(shù)據(jù)速率： 67MHz
訪問時(shí)間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V3612L15PF8
3
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-Empty
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
Flag
(Port A) the FIFO2 is less than or equal to the value in the offset register, X.
AEB
PortBAlmost-Empty
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
Flag
(PortB) FIFO1 is less than or equal to the value in the offset register, X.
AFA
Port A Almost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Flag
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
AFB
Port B Almost-Full
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
Flag
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
B0-B35
Port B Data.
I/O
36-bit bidirectional data port for side B.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-
HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-
HIGH transition of CLKB.
CSA
Port A Chip Select
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA
Port A Empty Flag
O
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty,
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register
when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
Port B Empty Flag
O
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is
(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA
Port A Full Flag
O
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full,
(Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFB
Port B Full Flag
O
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB
is LOW, FIFO2 is full,
(Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
FS1, FS0
Flag Offset Selects
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
Select
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output,
and a LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH
when the device is reset.
PIN DESCRIPTION
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