19
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 12. Timing for AEA
AEA
AEA when FIFO2 is Almost Empty
Figure 14. Timing for AFB
AFB
AFB when FIFO2 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 13. Timing for AFA
AFA
AFA when FIFO1 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
AEA
CLKB
ENA
4659 drw 15
ENB
CLKA
2
1
tENS2
tENH2
tSKEW2
tPAE
tENS2
tENH2
(X+1) Words in FIFO2
X Words in FIFO2
(1)
AFA
CLKA
ENB
4659 drw 16
ENA
CLKB
12
tSKEW2
tENS2
tENH2
tPAF
tENS2
tENH2
tPAF
[64-(X+1)] Words in FIFO1
(64-X) Words in FIFO1
(1)
AFB
CLKB
ENA
4659 drw 17
ENB
CLKA
12
tSKEW2
tENS2
tENH2
tPAF
tENS2
tENH2
tPAF
[64-(X+1)] Words in FIFO2
(64-X) Words in FIFO2
(1)