參數(shù)資料
型號: IDT72V3613L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/25頁
文件大?。?/td> 0K
描述: IC FIFO CLOCK 64X36 15NS 120TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲容量: 2.3K(64 x 36)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3613L15PF8
2
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
DESCRIPTION (CONTINUED)
PIN CONFIGURATION
NOTES:
1. Pin 1 idenifier in corner.
2. NC = No internal connection
TQFP (PNG120, order code: PF)
TOP VIEW
4661 drw 02
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EF
AE
NC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AF FF
CSA ENA
CLKA
W/
R
A
V
CC
PGA
PEFA MBF2 MBA
FS
1
FS
0
ODD/
EVEN
RST GND BE SW1 SW0 SIZ1
MBF1
SIZ0
PEFB PGB
V
CC
W/
R
B
CLKB
ENB
CSB NC
31
32
33 34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 51
52
53
54
55
56
57
58
59
60
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
36-bitmailboxregisters.Eachmailboxregisterhasaflagtosignalwhen new
mail has been stored. Parity is checked passively on each port and may be
ignoredifnotdesired.Paritygenerationcanbeselectedfordatareadfromeach
port.Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
The IDT72V3613 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a continuous (free-running) port clock by
enable signals. The continuous clocks for each port are independent of one
anotherandcanbeasynchronousorcoincident.Theenablesforeachportare
arrangedtoprovideasimpleinterfacebetweenmicroprocessorsand/orbuses
withsynchronousinterfaces.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronizedtotheportclock(CLKA)thatwritesdataintoitsarray.TheEmpty
Flag(EF)andAlmost-Empty(AE)flagoftheFIFOaretwo-stagesynchronized
to the port clock (CLKB) that reads data from its array.
The IDT72V3613 is characterized for operation from 0
°C to 70°C. This
deviceisfabricatedusinghighspeed,submicronCMOStechnology.
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