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參數(shù)資料
| 型號： | IDT72V3613L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 25/25頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO CLOCK 64X36 15NS 120TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3613L15PF8 |
9
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
TABLE 3 – PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
SIZ1, SIZ0
CLKB
Data B (B0-B35) I/O
Port Function
H
X
Input
None
L
H
L
X
Input
None
L
H
One,bothLOW
↑
Input
None
L
H
BothHIGH
↑
Input
Mail2write
L
One,bothLOW
X
Output
None
L
H
One,bothLOW
↑
Output
FIFO read
L
BothHIGH
X
Output
None
L
H
BothHIGH
↑
Output
Mail1 read (set MBF1 HIGH)
FUNCTIONALDESCRIPTION
RESET (RST)
TheIDT72V3613isresetbytakingtheReset(RST)inputLOWforatleast
four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions.TheResetinputcanswitchasynchronouslytotheclocks. Adevice
resetinitializestheinternalreadandwritepointersoftheFIFOandforcesthe
FullFlag(FF)LOW,theEmptyFlag(EF)LOW,theAlmost-Emptyflag(AE)LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH
transitions of CLKA. The device must be reset after power up before data is
writtentoitsmemory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-EmptyOffsetregister(X)withthevalueselectedbytheFlagSelect(FS0,
FS1)inputs. ThevaluesthatcanbeloadedintotheregisterareshowninTable
1.SeeFigure5forrelevantFIFOResetandpresetvalueloadingtimingdiagram.
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbytheport-AChip
Select (CSA) and the port-A Write/Read select (W/RA).TheA0-A35outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW.
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
Input
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO write
LH
H
↑
Input
Mail1write
L
X
Output
None
LL
H
L
↑
Output
None
L
H
X
Output
None
LL
H
↑
Output
Mail2 read (set MBF2 HIGH)
TABLE 2 – PORT A ENABLE FUNCTION TABLE
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTYFLAG
OFFSET REGISTER (X)
HH
↑
16
HL
↑
12
LH
↑
8
LL
↑
4
TABLE 1 – FLAG PROGRAMMING
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FF is HIGH (see Table 2). The relevant FIFO write timing diagram
can found in Figure 6.
ThestateoftheportBdata(B0-B35)outputsiscontrolledbytheportB
Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35
outputsareinthehigh-impedancestatewheneitherCSBorW/RBisHIGH.The
B0-B35 outputs are active when both CSB and W/RB are LOW. Data is read
fromtheFIFOtotheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKBwhen
CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or
SIZ1isLOW(seeTable3).RelevantFIFOreadtimingdiagramstogetherwith
Bus-Matching, Endian select and Byte-swapping operation can be found in
Figures 7, 8 and 9.
Thesetupandhold-timeconstraintstotheportclocksfortheportChipSelects
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata
outputs. IfaportenableisLOWduringaclockcycle,theport’sChipSelectandWrite/
Readselectcanchangestatesduringthesetupandholdtimewindowofthecycle.
SYNCHRONIZED FIFO FLAGS
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages.
This is done to improve the flags’ reliability by reducing the probability of
metastableeventsontheiroutputswhenCLKAandCLKBoperateasynchro-
nouslytooneanother. FFandAFaresynchronizedtoCLKA. EFandAEare
synchronizedtoCLKB. Table4showstherelationshipofeachportflagtothe
level of FIFO fill.
EMPTY FLAG (EF)
TheFIFOEmptyFlagissynchronizedtotheportclockthatreadsdatafrom
itsarray(CLKB). WhentheEFisHIGH,newdatacanbereadtotheFIFOoutput
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads
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| IDT72V3613L15PQF | 功能描述:IC FIFO CLOCK 64X36 15NS 132PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L20PF | 功能描述:IC FIFO CLOCK 64X36 20NS 120TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L20PF8 | 功能描述:IC FIFO CLOCK 64X36 20NS 120TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L20PQF | 功能描述:IC FIFO CLOCK 64X36 20NS 132PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3614L12PF | 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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