IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x" />
參數(shù)資料
型號(hào): IDT72V3614L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 20NS 120QFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問(wèn)時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3614L20PF8
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
25
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last
word or byte of the long word, respectively.
Figure 16. FFA
FFA
FFA Flag Timing and First Available Write when FIFO1 is Full.
CSB
EFB
SIZ1,
SIZ0
ENB
B0 - B35
CLKB
FFA
CLKA
CSA
4663 drw 16
W
RA
12
A0 - A35
MBA
ENA
tCLK
tCLKH
tCLKL
tENS
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tENS
tDS
tENH
tDH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W/
RB LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
tWFF
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