IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x " />
參數(shù)資料
型號(hào)： IDT72V3614L20PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 27/32頁(yè)
文件大小： 0K
描述： IC FIFO 64X36X2 20NS 120QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 4.6K（64 x 36 x2）
數(shù)據(jù)速率： 50MHz
訪問(wèn)時(shí)間： 20ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 72V3614L20PF8
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
4
PIN DESCRIPTION (Continued)
Symbol
Name
I/O
Description
MBF2
Mail2Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
Flag
mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/
Odd/Even
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
EVEN
ParitySelect
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
PEFA
Port A Parity
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8,
Error Flag
(Port A) A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type
of parity checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA
LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs.
PEFB
Port B Parity
O
When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8,
Error Flag
(Port B) B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. A byte is valid
when it is used by the bus size selected for Port B. The type of parity checked is determined by the state of
the ODD/EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB
LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-
B35inputs.
PGA
Port A Parity
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected
Generation
by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
PGB
Port B Parity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected
Generation
by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The
generated parity bits are output in the most significant bit of each byte.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA,
AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0
inputstoselectAlmost-FullandAlmost-Emptyflagoffsets.
SIZ0, SIZ1 Port B Bus
I
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to-HIGH
SizeSelects
(Port B) transition of CLKB implements the latched statesasaport B bus size. Port B bus sizes can be long word,
word or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit write or
read.
SW0,SW1 Port B Byte
I
At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by SW0
SwapSelect
(Port B) and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping
ispossiblewithanybus-sizeselection.
W/RA
PortAWrite/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
ReadSelect
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
W/RB
PortBWrite/
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
ReadSelect
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
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IDT72V3622L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC BIFIFO 256X36X2 10NS 120-TQFP
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