IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x" />
參數(shù)資料
型號: IDT72V3614L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/32頁
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 20NS 120QFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3614L20PF8
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
6
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3614 with CLKA and CLKB set
tofS.Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnectedtonormalize
thegraphtoazero-capacitanceload.Oncethecapacitiveleadperdata-outputchannelisknown,thepowerdissipationcanbecalculatedwiththeequationbelow.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3614 can be calculated by:
PT = VCC x ICC(f) +
Σ(CL x VOH2 x fo)
N
where:
N
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size)
CL
=
outputcapacitanceload
fo
=
switchingfrequencyofanoutput
VOH
=
outputhighlevelvoltage
When no reads or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is calculated
by:
PT=VCC x fS x 0.025 mA/MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010
20
30
40
50
60
70
0
25
50
75
100
125
150
VCC = 3.3V
fS
Clock Frequency MHz
ICC(f)
Supply
Current
mA
fdata = 1/2 fS
TA = 25
°C
CL = 0 pF
VCC = 3.0V
4663 drw 04
VCC = 3.6V
80
90
175
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