IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36 " />
參數(shù)資料
型號: IDT72V3632L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 23/29頁
文件大?。?/td> 0K
描述: IC BIFIFO 512X36X2 10NS 120-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲容量: 36.8K(512 x 36 x 2)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3632L10PF8
3
COMMERCIAL TEMPERATURERANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong-
word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
wordsdoesnecessitateaformalreadrequest).ThestateoftheFWFTpinduring
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).
TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates
whether or not the FIFO memory is empty. FF shows whether the memory is
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough
mode. IR indicates whether or not the FIFO has available memory locations.
ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe
presence of valid data on the outputs.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and
aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory. AFAandAFBindicate
when the FIFO contains more than a selected number of words.
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport
clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are
two-stage synchronized to the port clock that reads data from its array.
ProgrammableoffsetsforAEA,AEB,AFAandAFBareloaded byusingPort
A.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEBthreshold
can be set at 8, 16 or 64 locations from the empty boundary and the AFAand
AFBthresholdcanbesetat8,16or64locationsfromthefullboundary.Allthese
choices are made using the FS0 and FS1 inputs during Reset.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V3622/72V3632/72V3642arecharacterizedforoperationfrom
0oC to 70oC. Industrial temperature range (-40οC to +85οC) is available by
special order. They are fabricated using high speed, submicron CMOS
technology.
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