IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERC" />
參數(shù)資料
型號(hào): IDT72V3632L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 6/29頁(yè)
文件大小: 0K
描述: IC BIFIFO 512X36X2 10NS 120-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 36.8K(512 x 36 x 2)
數(shù)據(jù)速率: 100MHz
訪問(wèn)時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3632L10PF8
14
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
RST1
FFA/IRA
AEB
AFA
MBF1
CLKB
EFB/ORB
FS1,FS0
4660 drw 04
tRSTS
tRSTH
tFSH
tFSS
tWFF
tREF
tRSF
0,1
tRSF
tFWS
FWFT
4660 drw 05
CLKA
RST1,
RST2
FFA/IRA
CLKB
FFB/IRB
A0 - A35
FS1,FS0
ENA
tFSS
tFSH
tWFF
tENH
tENS2
tSKEW1
tDS
tDH
tWFF
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
1
2
(1)
12
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