參數(shù)資料
型號: IDT72V3650L15PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/46頁
文件大?。?/td> 0K
描述: IC FIFO SS 2048X36 15NS 128-TQFP
標準包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V3650L15PFI8
1
OCTOBER 22, 2008
DSC-4667/16
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
3.3V HIGH-DENSITY SUPERSYNC II 36-BIT FIFO
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
IDT72V3640, IDT72V3650
IDT72V3660, IDT72V3670
IDT72V3680, IDT72V3690
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Choose among the following memory organizations:Commercial
IDT72V3640
1,024 x 36
IDT72V3650
2,048 x 36
IDT72V3660
4,096 x 36
IDT72V3670
8,192 x 36
IDT72V3680
16,384 x 36
IDT72V3690
32,768 x 36
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (PBGA Only)
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Pin to Pin compatible to the higher density of IDT72V36100 and
IDT72V36110
Big-Endian/Little-Endian user selectable byte representation
5V input tolerant
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (PBGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
High-performance submicron CMOS technology
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK/WR
D0 -Dn (x36, x18 or x9)
LD
MRS
REN
RCLK/RD
OE
Q0 -Qn (x36, x18 or x9)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4667 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
RM
ASYR
ASYW
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
*
*Available on the PBGA package only.
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