IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號: IDT72V3650L15PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/46頁
文件大?。?/td> 0K
描述: IC FIFO SS 2048X36 15NS 128-TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V3650L15PFI8
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
PIN CONFIGURATIONS
TQFP (PK128-1, order code: PF)
TOP VIEW
DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are
exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories
with clocked read and write controls and a flexible Bus-Matching x36/x18/x9
data flow. These FIFOs offer several key user benefits:
Flexible x36/x18/x9 Bus-Matching on both read and write ports
The period required by the retransmit operation is fixed and short.
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
Asynchronous/Synchronous translation on the read or write ports
High density offerings up to 1 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(
WEN)input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
NOTE:
1. DNC = Do Not Connect.
VCC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IW
D35
D34
D33
D32
D31
VCC
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
D21
D20
D19
D18
GND
D17
D16
D15
VCC
D13
D12
GND
D11
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
Q35
Q34
Q33
Q32
GND
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
Q15
Q14
Q13
Q12
GND
Q11
Q10
INDEX
WEN
SEN
DNC(1)
D14
VCC
4667 drw02a
DNC(1)
RT
REN
RCLK
PAE
PFM
EF
/OR
RM
GND
V
CC
BM
IP
BE
FS1
GND
HF
FS0
OW
GND
PAF
V
CC
FF
/IR
FWFT/SI
LD
MRS
PRS
WCLK
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
D10
D9
D8
D7
D
6
GND
D5
D4
D2
D1
D0
GND
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q
6
Q7
Q
9
104
103
Q8
V
CC
V
CC
D3
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IDT72V3650L6PF 功能描述:IC FIFO SS 2048X36 6NS 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
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