IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號(hào): IDT72V3650L15PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 46/46頁(yè)
文件大小: 0K
描述: IC FIFO SS 2048X36 15NS 128-TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V3650L15PFI8
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS(1)— SYNCHRONOUS TIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0
°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 7-5ns and 15ns speed grades are available as standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns, the minimum for tA, tOE, and tOHZ is 2ns.
Commercial
Com’l & Ind’l(2)
Commercial
Com’l & Ind’l(2)
PBGA & TQFP
TQFP Only
IDT72V3640L6
IDT72V3640L7-5
IDT72V3640L10
IDT72V3640L15
IDT72V3650L6
IDT72V3650L7-5
IDT72V3650L10
IDT72V3650L15
IDT72V3660L6
IDT72V3660L7-5
IDT72V3660L10
IDT72V3660L15
IDT72V3670L6
IDT72V3670L7-5
IDT72V3670L10
IDT72V3670L15
IDT72V3680L6
IDT72V3680L7-5
IDT72V3680L10
IDT72V3680L15
IDT72V3690L6
IDT72V3690L7-5
IDT72V3690L10
IDT72V3690L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
166
133.3
100
66.7
MHz
tA
Data Access Time(5)
14
1(5)
51(5)
6.5
1(5)
10
ns
tCLK
Clock Cycle Time
6
7.5
10
15
ns
tCLKH
Clock High Time
2.7
3.5
4.5
6
ns
tCLKL
Clock Low Time
2.7
3.5
4.5
6
ns
tDS
DataSetupTime
2
2.5
3.5
4
ns
tDH
Data Hold Time
0.5
0.5
0.5
1
ns
tENS
Enable Setup Time
2
2.5
3.5
4
ns
tENH
Enable Hold Time
0.5
0.5
0.5
1
ns
tLDS
LoadSetupTime
3
3.5
3.5
4
ns
tLDH
Load Hold Time
0.5
0.5
0.5
1
ns
tRS
Reset Pulse Width(3)
10
10
10
15
ns
tRSS
ResetSetupTime
15
15
15
15
ns
tRSR
Reset Recovery Time
10
10
10
15
ns
tRSF
Reset to Flag and Output Time
15
15
15
15
ns
tRTS
RetransmitSetupTime
3
3.5
3.5
4
ns
tOLZ
Output Enable to Output in Low Z(4)
0—
0
0—
ns
tOE
Output Enable to Output Valid(5)
14
1(5)
61(5)
8ns
tOHZ
Output Enable to Output in High-Z(4,5)
14
1(5)
61(5)
8ns
tWFF
Write Clock to
FF or IR
—4
—5
—6.5
10
ns
tREF
Read Clock to
EF or OR
—4
—5
—6.5
10
ns
tPAFA
Clock to Asynchronous Programmable Almost-Full Flag
10
12.5
16
20
ns
tPAFS
Write Clock to Synchronous Programmable Almost-Full Flag
4
5
6.5
10
ns
tPAEA
Clock to Asynchronous Programmable Almost-Empty Flag
10
12.5
16
20
ns
tPAES
Read Clock to Synchronous Programmable Almost-Empty Flag
4
5
6.5
10
ns
tHF
Clock to
HF
10
12.5
16
20
ns
tSKEW1
Skew time between RCLK and WCLK for
EF/OR and FF/IR
4—
5—
7
9—
ns
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
5—
7—
10
14
ns
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