參數(shù)資料
型號(hào): IDT72V3676L10PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/39頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 16384X36 10NS 128QFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步
存儲(chǔ)容量: 576K(16K x 36)
數(shù)據(jù)速率: 100MHz
訪問(wèn)時(shí)間: 10ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤(pán)
其它名稱(chēng): 72V3676L10PF
2009
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4665/5
IDT72V3656
IDT72V3666
IDT72V3676
1
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
FEBRUARY 2009
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Memory storage capacity:
IDT72V3656
2,048 x 36 x 2
IDT72V3666
4,096 x 36 x 2
IDT72V3676
8,192 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Loopback mode on Port A
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V parts,
IDT723656/723666/723676
Pin compatible to the lower density parts, IDT72V3626/3636/3646
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
LOOP
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
WENC
Port-C
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
13
EFB/ORB
AEB
18
FFC/IRC
AFC
B0-B17
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
4665 drw01
36
Output
Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
C0-C17
CLKB
RENB
CSB
MBB
Port-B
Control
Logic
Common
Port
Control
Logic
(B and C)
BE
SIZEB
SIZEC
CLKC
MBC
36
Input
Bus-
Matching
FIFO1 and
FIFO2
Retransmit
Logic
RT1
RT2
RTM
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