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參數(shù)資料
| 型號(hào)： | IDT72V3676L10PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 16384X36 10NS 128QFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲(chǔ)容量： | 576K（16K x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時(shí)間： | 10ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3676L10PF |
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11
COMMERCIALTEMPERATURERANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT72V3656/72V3666/72V3676 undergoes a complete reset
by taking its associated Master Reset (
MRS1)inputLOWforatleastfourPort
A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The
FIFO2 memory undergoes a complete reset by taking its associated Master
Reset (
MRS2) input LOW for at least four Port A Clock (CLKA) and four Port
CClock(CLKC)LOW-to-HIGHtransitions. TheMasterResetinputscanswitch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag (
FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and the Almost-
Fullflag(
AFA,AFC)HIGH. AMasterResetalsoforcestheassociatedMailbox
Flag (
MBF1, MBF2) of the parallel mailbox register HIGH. After a Master
Reset,theFIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles.
Then the FIFO is ready to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (
MRS1) input
latchesthevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhich
bytes are transferred through Ports B and C. It also latches the values of the
FlagSelect (FS0,FS1andFS2)inputsforchoosingtheAlmost-FullandAlmost-
Emptyoffsetsandprogrammingmethod.
A LOW-to-HIGH transition on the FIFO2 Master Reset (
MRS2)clearsthe
flagoffsetregistersofFIFO2(X2,Y2). ALOW-to-HIGHtransitionontheFIFO2
Master Reset (
MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetsandprogrammingmethod(fordetailsseeTable
1, Flag Programming, and Almost-Empty and Almost-Full flag offset program-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
Note that MBC must be HIGH during Master Reset (until
FFA/IRA and
FFC/IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master
Reset.
PARTIAL RESET (
PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking
its associated Partial Reset (
PRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(
PRS2)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGHtransitions.TheRTMpinmustbeLOWduringthetimeofpartial
reset.ThePartialResetinputscanswitchasynchronouslytotheclocks.APartial
Reset initializes the internal read and write pointers and forces the Full/Input
Ready flag (
FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/
ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Full flag (
AFA, AFC) HIGH. A Partial Reset also forces the Mailbox
Flag (
MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial
Reset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
RETRANSMIT (
RT1, RT2)
The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (
RT1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit(
RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
C Clock (CLKC) LOW-to-HIGH transitions. The Retransmit initializes the read
pointer of FIFO1 to the first memory location.
The RTM pin must be HIGH during the time of Retransmit. Note that the
RT1inputismuxedwiththe PRS1 input,thestateoftheRTMpindetermining
whether this pin performs a Retransmit or Partial Reset. Also, the
RT2inputis
muxed with the
PRS2input,thestateoftheRTMpindeterminingwhetherthis
pin performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmittimingdiagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
writtentoPortCorreadfromPortB.Thisselectiondeterminestheorderbywhich
bytes (or words) of data are transferred through those ports. For the following
illustrations, note that both ports B and C are configured to have a byte (or a
word) bus size.
A HIGH on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
is moving in the direction from Port A to Port B, the least significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (
MRS1, MRS2) input is
HIGH, a HIGH on the BE/
FWFTinputduringthenextLOW-to-HIGHtransition
ofCLKA(forFIFO1)andCLKC(forFIFO2)willselectIDTStandardmode.This
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
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| IDT72V3676L10PF8 | 功能描述:IC FIFO 16384X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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