參數(shù)資料
型號(hào)： IDT72V51443L7-5BB8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 37/50頁
文件大?。?/td> 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝： 1,000
類型： 多隊(duì)列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（17x17）
包裝： 帶卷 (TR)
其它名稱： 72V51443L7-5BB8
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
RCLK
OE
tOLZ
REN
RADEN
ESTR
WRADD
tAH
000 01111
tAS
RDADD
D0Q16
D0 Q16
111 xxxx0
D7 sect 1
110 00010
*A*
*B*
*C*
*D*
*E*
*F*
000 xxx1
tQH
tQS
tQH
tQS
tAH
tAS
tSTH
tSTS
tSTH
tSTS
5939 drw27
*AA*
0xxx xxxx
D0Sect2
Device 0
PAFn
Bus
PAFn
*BB*
*CC*
*DD*
*EE*
*FF*
tPAFLZ
1xxx xxxx
D0Sect2
tPAF
0xxx xxxx
D0Sect2
1xxx xxxx
D0Sect2
D0Sect2 0xxx xxxx
DXQuad y
Prev.
PAFn
DXQuad y
tPAFHZ
HIGH-Z
Device 0
PAF
HIGH - Z
tPAFLZ
tWAF
Qout
D6Q2
WX
Prev. Q
WD-M+1
tA
D0 sect2
FSTR
tA
WCLK
tSKEW3
WX +1
Prev. Q
12
D0 Q16
WEN
tENS
WADEN
tQH
tQS
tAH
tAS
tAH
tAS
WD - M + 2
tA
*G*
tA
D0 Q16
W0
D6 Q2
tENH
Din
tDS
tDH
tDS
tDH
tDS
tDH
Word Wy
D0 Q16
Wy+1
D0 Q16
Wy+2
D0 Q16
Figure 25.
PAFn - Direct Mode, Flag Operation
Cycle:
*A*
Queue 16 of device 0 is selected for read operations.
The last word in the output register is available on Qout.
OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Sector 2 of device 0 is selected for the
PAFn bus. The bus is currently providing status of a previously selected sector, Sect Y of device X.
*B*
Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*BB* Queue 16 of device 0 is selected on the write port.
The
PAFn bus is updated with the sector selected on the previous cycle, D0 Sect 2. PAF[7] is LOW showing the status of queue 16.
The
PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*C*
A new sector, Sect 1 of Device 7 is selected for the
PAFn bus.
Word, Wd-m+1 is read from Q16 D0 due to the FWFT operation. This read is at the
PAFn boundary of queue D0 Q16. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*CC*
PAFn continues to show status of Sect 2 D0.
*D*
No read operations occur,
REN is HIGH.
*DD*
PAF[7] goes HIGH to show that D0 Q16 is not almost empty due to the read on cycle *C*.
The active queue
PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q16.
*E*
Queue 2 of Device 6 is selected for write operations.
*EE* Word, Wy+1 is written into D0 Q16.
*F*
Word, Wd-m+2 is read out due to FWFT operation.
*FF*
PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q16 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q16.
*G*
Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
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IDT72V51446L6BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51446L7-5BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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