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| 型號： | IDT72V51443L7-5BB8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 50/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標準包裝： | 1,000 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V51443L7-5BB8 |
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9
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PAE
Programmable
LVTTL
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
Almost-EmptyFlag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAEn bus lines. This flag is
synchronized to RCLK.
PAEn
Programmable
LVTTL
Onthe16Qdevicethe
PAEnbusis8bitswide.ThisoutputbusprovidesPAEstatusof8queues(1sector),
Almost-EmptyFlagBus OUTPUT
within a selected device, having a total of 2 sectors. During queue read/write operations these outputs
provide programmable empty flag status, in either direct or polled mode. The mode of flag operation is
determined during master reset via the state of the FM input. This flag bus is capable of High-Impedance
state, this is important during expansion of multi-queue devices. During direct operation the
PAEnbusis
updated to show the
PAE statusofasectorofqueueswithinaselecteddevice.Selectionismadeusing
RCLK, ESTR and RDADD. During Polled operation the
PAEn bus is loaded with the PAE status of
multi-queue flow-control sectors sequentially based on the rising edge of RCLK.
PAF
Programmable
LVTTL
This pin provides the Almost-Full flag status for the queue that has been selected on the input port forwrite
Almost-FullFlag
OUTPUT
operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue is
almost-full.Thisflagoutputmaybeduplicatedononeofthe
PAFnbuslines.ThisflagissynchronizedtoWCLK.
PAFn
Programmable
LVTTL
On the 16Q device the
PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of
Almost-Full Flag Bus
OUTPUT
8 queues (1 sector), within a selected device, having a total of 2 sectors. During queue read/write
operations these outputs provide programmable full flag status, in either direct or polled mode. The mode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable
ofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirectoperation
the
PAFnbusisupdatedtoshowthePAFstatusofasectorofqueueswithinaselecteddevice.Selection
ismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthe
PAFnbusisloadedwith
the
PAF statusofmulti-queueflow-controlsectorssequentiallybasedontherisingedgeofWCLK.
PRS
PartialReset
LVTTL
APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
Q[17:0]
Data Output Bus
LVTTL
These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge
Qout
OUTPUT
of RCLK provided that
REN is LOW, OE is LOW and the queue is selected. Due to bus matching not all
outputs may be used, any unused outputs should not be connected.
RADEN
Read Address Enable
LVTTL
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
INPUT
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part
has been completed and
SENO has gone LOW.
RCLK
Read Clock
LVTTL
When enabled by
REN, the rising edge of RCLK reads data from the selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAEnflagsectortobeplacedonthePAEnbusduringdirectflagoperation.Duringpolledflagoperation
the
PAEnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.The PAE
and
OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are
based on RCLK. RCLK must be continuous and free-running.
RDADD
Read Address Bus
LVTTL
For the 16Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
[7:0]
INPUT
functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant4bitsofthebus,RDADD[3:0]
areusedtoaddress1of16possiblequeueswithinamulti-queuedevice.Addresspin,RDADD[4]provides
the user with a Null-Q address. If the user does not wish to address one of the 16 queues, a Null-Q can
be addressed using this pin. The Null-Q operation is discussed in more detail later. The most significant
3 bits, RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSb’s will address a device with the matching ID code. The address present
on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
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| IDT72V51443L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51446L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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