參數(shù)資料
型號(hào): IDT72V71660BB
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 0K
描述: IC DGTL SW 16382X16384 208-BGA
標(biāo)準(zhǔn)包裝: 12
系列: 72V
類型: 多路復(fù)用器
獨(dú)立電路: 4
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BGA
供應(yīng)商設(shè)備封裝: 208-PBGA(17x17)
包裝: 托盤
其它名稱: 72V71660BB
7
INDUSTRIAL TEMPERATURERANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL
TABLE 1 — CONSTANT THROUGHPUT
DELAY VALUE
TABLE 2 — VARIABLE THROUGHPUT
DELAY VALUE
NOTE: Unused STA and CH bits should be set to zero.
Delay for Constant Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
2.048Mb/s
32 + (32 – n) +m time-slots
4.096Mb/s
64 + (64 – n) +m time-slots
8.192Mb/s
128 + (128 – n) +m time-slots
16.384Mb/s
256 + (256 – n) +m time-slots
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number; n – input channel number)
m
≤≤≤≤≤ n+2
m > n+2
2.048Mb/s
32 – (n-m) time-slots
(m-n)time-slots
4.096Mb/s
64 – (n-m) time-slots
(m-n)time-slots
8.192Mb/s
128 – (n-m) time-slots
(m-n)time-slots
16.384Mb/s
256 – (n-m) time-slots
(m-n)time-slots
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
Location
1
STA5
STA4
STA3
STA2
STA1
STA0
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R
Data Memory
1
0
STA5
STA4
STA3
STA2
STA1
STA0
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R/W
Connection Memory
0
1
0
x
R/W
ControlRegister
0
1
0
1
x
R
Frame Align Register
0
1
0
x
R/W
Frame Offset Register 0
0
1
0
1
x
R/W
Frame Offset Register 1
0
1
0
1
0
x
R/W
Frame Offset Register 2
0
1
0
1
x
R/W
Frame Offset Register 3
0
1
0
1
0
x
R/W
Frame Offset Register 4
0
1
0
1
0
1
x
R/W
Frame Offset Register 5
0
1
0
1
0
x
R/W
Frame Offset Register 6
0
1
0
1
x
R/W
Frame Offset Register 7
0
1
0
x
R/W
Frame Offset Register 8
0
1
0
1
x
R/W
Frame Offset Register 9
0
1
0
1
0
x
R/W
Frame Offset Register 10
0
1
0
1
x
R/W
Frame Offset Register 11
0
1
0
x
R/W
Frame Offset Register 12
0
1
0
1
x
R/W
Frame Offset Register 13
0
1
0
x
R/W
Frame Offset Register 14
0
1
x
R/W
Frame Offset Register 15
Bits MOD1-0 Values in
ODE pin
OSB bit in Control
Output Status
Connection Memory
Register
1 and 1
Don’t Care
Per-channel
high-Impedance
Any, other than 1 and 1
0
high-Impedance
Any, other than 1 and 1
0
1
Enable
Any, other than 1 and 1
1
0
Enable
Any, other than 1 and 1
1
Enable
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