參數(shù)資料
型號(hào)： IDT72V71660BB
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 0K
描述： IC DGTL SW 16382X16384 208-BGA
標(biāo)準(zhǔn)包裝： 12
系列： 72V
類型： 多路復(fù)用器
獨(dú)立電路： 4
電壓電源： 單電源
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤
其它名稱： 72V71660BB
8
INDUSTRIAL TEMPERATURERANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 5 — CONTROL REGISTER (CR) BITS
Reset Value:
0000H.
BIT
NAME
DESCRIPTION
15
SRS
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
(SoftwareReset)
14
OEI
When1,theTX32-63/OEI0-31pinswillbeOEI0-31andreflecttheactiveorhigh-impedancestateoftheircorrespondingoutputdata
(OutputEnableIndication)
streams. When 0, this feature is disabled and these pins are used as output data streams TX32-63.
13
OEPOL
When1,aoneonanOutputEnableIndicationpindenotesanactivestateontheoutputdatastream;zeroonanOutputEnableIndication
(Output Enable Polarity)
pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes
an active state.
12
AOE
When 1, TX0-63 will behave as OEI0-63 accordingly. These outputs will reflect the active or high-impedance state of the
(All Output Enables)
correspondingoutputdatastreams(TX0-63)inanotherIDT72V71660ifprogrammedidentically. When0,theTSIoperatesinthenormal
switch mode.
11-10
Unused
Must be zero for normal operation.
9
MBP
When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits,
(Memory Block Program)
bit 14 and bit 15. When 0, this feature is disabled.
8-7
BPD1-0
These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature
(Block Programming
is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1,
Data)
the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the
Connection Memory are set to 0.
6
BPE
A zero to one transition of this bit enables the memory block programming function. Once the Block Programming Enable
(Begin Block
bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished,
ProgrammingEnable)
the Block Programming Enable, Memory Block Program and Block Programming Data1-0 bits will be reset to zero by the device
to indicate the operation is complete.
5
OSB
When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When
(Output Stand By)
either ODE = 1 or Output Stand By =1 the output serial streams drivers function normally.
4
SFE
AzerotoonetransitioninthisbitstartstheFrameEvaluationprocedure.WhentheCompleteFrameEvaluationbitintheFrameAlignment
(Start Frame Evaluation)
Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for
at least one frame.
3-2
Unused
Must be zero for normal operation.
1-0
DR1-0
DR1
DR0
DataRate
Master Clock
(DataRateSelect)
0
2.048Mb/s
4.096 MHz
0
1
4.096Mb/s
8.192 MHz
1
0
8.192Mb/s
16.384 MHz
1
16.384Mb/s
16.384 MHz
15
14
13
12
11
10
9876543210
SRS
OEI
OEPOL
AOE
0
MBP
BPD1
BPD0
BPE
OSB
SFE
0
DR1
DR0
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