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參數(shù)資料
| 型號： | IDT74ALVCH16903PA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 12-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 133K |
| 代理商： | IDT74ALVCH16903PA |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
7
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
125
—
125
—
125
—
MHz
tPLH
Propagation Delay, Buffer Mode
1
4.4
—
4.2
1.1
3.8
ns
tPHL
xAx to xYx
tPLH
Propagation Delay, Both Modes
1
5.7
—
4.9
1.4
4.4
ns
tPHL
CLK to
YERR
tPLH
Propagation Delay, Both Modes
1.2
8.6
—
7.9
1.7
6.6
ns
tPHL
CLK to PARI/O
tPLH
Propagation Delay, Both Modes
1
6.8
—
5.2
1.3
4.5
ns
tPHL
CLK to PARI/O
tPLH
Propagation Delay, Both Modes
1
5.9
—
5.8
1.3
4.9
ns
tPHL
Mode to xYx
tPLH
Propagation Delay, Register Mode
1
6.1
—
5.5
1.2
4.8
ns
tPHL
CLK to xYx
1
5.9
—
4.9
1.2
4.6
tPLH
Propagation Delay, Both Modes
1
3.6
—
4.2
1.9
4
ns
OE to YERR
tPHL
Propagation Delay, Both Modes
1.2
5.1
—
4.9
1.5
4.2
ns
OE to YERR
tPZH
Output Enable Time, Both Modes
1.1
6.5
—
6.4
1.4
5.4
ns
tPZL
OE to xYx
tPZH
Output Enable Time, Both Modes
1
5.6
—
6
1
4.8
ns
tPZL
PAROE to PARI/O
tPHZ
Output Disable Time, Both Modes
1
6.4
—
5.2
1.7
5
ns
tPLZ
OE to xYx
tPHZ
Output Disable Time, Both Modes
1
3.2
—
3.8
1.2
3.8
ns
tPLZ
PAROE to PARI/O
tSU
Set-up Time, Register Mode, 1A-12A before CLK
↑
1.7
—
1.9
—
1.45
—
ns
tSU
Set-up Time, Buffer Mode, 1A to 10A before CLK
↑
5.9
—
5.2
—
4.4
—
ns
tSU
Set-up Time, Register Mode, APAR before CLK
↑
1.2
—
1.5
—
1.3
—
ns
tSU
Set-up Time, Buffer Mode, APAR before CLK
↑
4.6
—
3.6
—
3.1
—
ns
tSU
Set-up Time, Both Modes, PARI/O before CLK
↑
2.4
—
2
—
1.7
—
ns
tSU
Set-up Time, Buffer Mode, 11A/
YERREN before CLK
↑
2
—
1.9
—
1.6
—
ns
tSU
Set-up Time, Register Mode,
CLKEN before CLK
↑
2.5
—
2.6
—
2.2
—
ns
tH
Hold Time, Register Mode, 1A-12A after CLK
↑
0.4
—
0.25
—
0.55
—
ns
tH
Hold Time, Buffer Mode, 1A-10A after CLK
↑
0.25
—
0.25
—
0.25
—
ns
tH
Hold Time, Register Mode, APAR after CLK
↑
0.7
—
0.4
—
0.7
—
ns
tH
Hold Time, Buffer Mode, APAR after CLK
↑
0.25
—
0.25
—
0.25
—
ns
tH
Hold Time, Register Mode, PARI/O after CLK
↑
0.25
—
0.25
—
0.4
—
ns
tH
Hold Time, Buffer Mode, PARI/O after CLK
↑
0.25
—
0.25
—
0.5
—
ns
tH
Hold Time, Buffer Mode, 11A/
YERREN after CLK
↑
0.25
—
0.25
—
0.4
—
ns
tH
Hold Time, Register Mode,
CLKEN after CLK
↑
0.25
—
0.5
—
0.4
—
ns
tW
Pulse Width, CLK
↑
3—
3
—
3
—
ns
tSK(O)
Output Skew(2)
—
————
500
ps
SWITCHING CHARACTERISTICS(1)
NOTES:
1.
See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
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