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參數(shù)資料
| 型號： | IDT74FCT88915TTCPYG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | GREEN, SSOP-28 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大小： | 108K |
| 代理商： | IDT74FCT88915TTCPYG |
9
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
When the PLL_EN pin is LOW, the PLL is bypassed and the FCT88915TT
is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q
output is inverted from the selected SYNC input, and the Q outputs are divide-
by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-
by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-
by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A recommended test
configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie
PLL_EN and REF_SEL together and connect them to the test select logic.
This functionality is needed since most board-level testers run at 1 MHz or
below, and the FCT88915TT cannot lock onto that low of an input frequency.
In the test mode described above, any test frequency test can be used.
Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication
and Low Board-to-Board skew
CMMU
CPU
CMMU
CPU
CMMU
PLL
2f
PLL
2f
CPU
CARD
CPU
CARD
SYSTEM
CLOC K
SOURCE
FCT88915TT
DISTRIBU TE
CLOCK @ f
CLOCK @ 2f
at point of use
ME MO RY
CONTROL
PLL
2f
ME MO RY
CAR DS
FCT88915TT
CLOCK
@f
CLOC K @ 2f
at point of use
FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY
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