- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67714 > IDT74FCT88915TTCPYG (INTEGRATED DEVICE TECHNOLOGY INC) FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 PDF資料下載
參數(shù)資料
| 型號： | IDT74FCT88915TTCPYG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | GREEN, SSOP-28 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TTCPYG |
4
COMMERCIALTEMPERATURERANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply Current
VCC = Max.
—
0.5
1.5
mA
TTL Inputs HIGH
VIN = VCC –2.1V(3)
ICCD
Dynamic Power Supply
VCC = Max.
VIN = VCC
—
0.5
0.7
mA/
Current(4)
All Outputs Open
VIN = GND
MHz
CPD
Power Dissipation Capacitance
50% Duty Cycle
—
25
40
pF
IC
Total Power Supply Current(5,6)
VCC = Max.
—
65
80
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50pF.
All other outputs open.
VCC = Max.
—
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50
Ω
Thevenin termination. All other outputs open.
PD1
Power Dissipation
50
Ω Thevenin termination@33MHz
—
120
—
mW
PD2
Power Dissipation
50
Ω Paralell termination to GND @ 33MHz
—
300
—
mW
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC +
ΔICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
ILOAD = Dynamic Current due to load.
Max.(2)
Symbol
Parameter
Min.
55
70
100
133
Unit
f2Q
Operating frequency 2Q Output
40
55
70
100
133
MHz
fQ
Operating frequency Q0-Q4,
Q5Outputs
20
27.5
35
50
66.7
MHz
fQ/2
Operating frequency Q/2 Output
10
13.75
17.5
25
33.3
MHz
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
OUTPUT FREQUENCY SPECIFICATIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT88915TTBJG8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| IDT74FCT88915TT133PY8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74FCT88915TT70PY8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74SSTU32864GBF | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| IDT74SSTU32864CBF8 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FST163211PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST163233PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST16323PA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST163244DPF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FST163244PA | 制造商:INT_DEV_TECH 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。