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參數(shù)資料
| 型號： | IDT77105L25TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) for 25.6 Mbps ATM Networks |
| 中文描述： | ATM NETWORK INTERFACE, PQFP64 |
| 封裝： | 10 X 10 MM, STQFP-64 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 335K |
| 代理商： | IDT77105L25TF |
13 of 24
September 11, 2000
IDT77105
1. Assert TxFull, via register 0x02, Bit 7. This stops the 77105 from
receiving more data, and prevents the complete assembly of a
cell for transmission.
2. Enter desired loopback mode.
3. De-assert TxFull using 0x02, Bit 7. The previously 'interrupted'
cell will continue to be assembled in the transmit FIFO; on
completion, it will be transmitted, as selected via the loopback
mode. If this partial cell should be discarded, assertion of TxSOC
will clear this 'short' cell from the internal FIFO, and normal oper-
ation will resume.
Entering Loopback (Cell Mode)
Under UTOPIA specification, cell transfer is initiated via the TxCLAV
control, which indicates that the transmission device can receive an
entire 53 byte cell for transmission. Therefore, a complete cell will auto-
matically be received and transmitted by the 77105, even after TxCLAV
assertion is inhibited:
1. De-assert TxCLAV, using 0x02, Bit 7. As described above, under
normal UTOPIA operation it is assumed that the remainder of the
cell will continue to be shipped to the 77105.
2. After waiting for complete cell to be transmitted, enable desired
loopback mode. If loopback is entered prior to complete cell
receipt, the cell will be looped back.
3. Re-assert TxCLAV using 0x02, Bit 7.
Exiting Loopback (Byte and Cell Modes)
The same conditions and concerns exist for exiting loopback, as for
entering these modes. Therefore, follow the above instructions, except
replace step #2 with 'disable loopback mode'.
2. Counters
Several condition counters are provided to assist external systems
(e.g. software drivers) in evaluating communications conditions. It is
anticipated that these counters will be polled from time-to-time (user
selectable) to evaluate performance.
!
Symbol Error Counter
–
8 bit counter
–
counts all undefined 5 bit symbols in received data stream
!
TxCell Counter
–
16 bit
–
counts all transmitted cells
!
RxCell Counter
–
16 bit counter
–
counts all received cells
!
Receive HEC Error Counter
–
5 bit counter
–
counts all received HEC errors
Figure 9 Normal Mode
Figure 10 PHY Loopback
Figure 11 Line Loopback
25 Mbps TC
PMD
Line
Interface
Upstream System
3445 drw 12
IDT77105
Upstream System
25 Mbps TC
PMD
Line
Interface
3445 drw 13
IDT77105
Upstream System
25 Mbps TC
PMD
Line
Interface
3445 drw 14
IDT77105
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| IDT77105L25TFI | PHY (TC-PMD) for 25.6 Mbps ATM Networks |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77105L25TFI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77155L155PX | 制造商:INT_DEV_TECH 功能描述: |
| IDT77201L25PF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77211L155PQF | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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