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參數(shù)資料
| 型號： | IDT77105L25TF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) for 25.6 Mbps ATM Networks |
| 中文描述： | ATM NETWORK INTERFACE, PQFP64 |
| 封裝： | 10 X 10 MM, STQFP-64 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 335K |
| 代理商： | IDT77105L25TF |
15 of 24
September 11, 2000
IDT77105
Figure 14 Multi-PHY Receive Waveform
PHY to Magnetics interface
Figure 21 provides the appropriate connection scheme to the Magnetics Module. The set of values provided will ensure the return Loss specifica-
tion is met.
Status and Control Register List
Nomenclature
R/W = register may be read and written via the utility bus;
R-only or W-only = register may be read-only or write-only via the utility bus;
sticky = register bit is cleared after the register containing it is read.
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
Master Control Register
Address: 0x00
Master Type Initial State
Function
Bit 7
R/W
0
UPLO
Controls pin 11, User Programmable Output Latch. Note that the polarity of pin 11 is opposite the polarity of this register bit.
Bit 6
R/W
0 = disabled
Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid symbol or HEC error (if enabled)), the cell will be discarded before
entering the receive FIFO.
Bit 5
R/W
0 = disabled
Enable Cell Error Interrupts Only
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only ‘Received Cell Error’ to trigger an interrupt.
Received Cell Errors are: short cell, invalid symbol and HEC error.
Bit 4
R/W
0 = disabled
Transmit Data Parity Check
Enable checking of TxData[7:0] parity against TxParity.
Bit 3
R/W
1 = enabled
Discard Received Idle Cells
Enable discarding of received idle (VPI/VCI = 0) cells. There is no indication when such a discard takes place.
Bit 2
R/W
0 = disabled
Halt Tx
Halts transmission of data and forces both TxD+/- signals to a logic low state.
Bit 1
R/W
0 = cell mode
UTOPIA mode select:
0 = cell mode, 1 = byte mode.
Bit 0
R/W
1 = enabled
Enable Interrupt Pin (Interrupt Mask Bit)
Enables interrupt output pin. If cleared, INT (pin 53 is always high. If set, INT will drive low when an interrupt occurs.
RxClk
RxSOC
RxEnb
RxData
H1
H2
P48
X
3445 drw 17
H1
RxClav
X
X
Z
Z
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77105L25TFI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77155L155PX | 制造商:INT_DEV_TECH 功能描述: |
| IDT77201L25PF | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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