參數(shù)資料
型號: IDT77105L25TF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 數(shù)字傳輸電路
英文描述: PHY (TC-PMD) for 25.6 Mbps ATM Networks
中文描述: ATM NETWORK INTERFACE, PQFP64
封裝: 10 X 10 MM, STQFP-64
文件頁數(shù): 20/24頁
文件大小: 335K
代理商: IDT77105L25TF
20 of 24
September 11, 2000
IDT77105
Figure 18 TxOSC and Reset Timing
Figure 19 Utility Bus Read Cycle
Utility Bus Read Cycle Utility Bus Write Cycle
Name
Min.
Max.
Unit
Comment
Name
Min.
Max.
Unit
Comment
Tas
10
ns
Address setup to ALE
Tapw
10
ns
ALE min pulse width
Tcsrd
0
ns
Chip select to read enable
Tas
10
ns
Address set up time to ALE
Tah
5
ns
Address hold to ALE
Tah
5
ns
Address hold time to ALE
Tapw
10
ns
ALE min pulse width
Tcswr
0
ns
CS Assert to WRB
Ttria
0
ns
Address tri-state to RDB assert
Twrpw
20
ns
Min. WRB pulse width
Trdpw
20
ns
Min. RDB pulse width
Tdws
20
ns
Write Data set up time
Tdh
0
ns
Data Valid hold time
Tdwh
10
ns
Write Data hold time
Tch
0
ns
RDB deassert to CS deassert
Tch
0
ns
WRB deassert to CS deassert
Ttird
10
ns
RDB deassert to data tristate
Taw
20
ns
ALE low to end of write
Trd
5
18
ns
Read Data access
Tar
5
ns
ALE low to start of read
Trdd
0
ns
Start of read to Data low-Z
3445 drw 29
TxOSC
RESET
Trpw
Tcyc
Tch
Tcl
.
3445 drw 21
CS
RDB
ALE
Tah
Tas
Tapw
Tch
Trdd
Trdpw
ADDR/DATA
(output)
Tdh
Trd
Ttrid
Tcsrd
Address
Data
Tar
ADDR/DATA
(input)
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