- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377484 > IDT77301L12PFI (INTEGRATED DEVICE TECHNOLOGY INC) UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO PDF資料下載
參數(shù)資料
| 型號： | IDT77301L12PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 3/29頁 |
| 文件大小： | 342K |
| 代理商： | IDT77301L12PFI |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
3
IDT77301
UtopiaFIFO 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO Commercial and Industrial Temperature Ranges
)*&+
Symbol
Name
I/O
Description
1-2, 4-8,
10, 100
DATA-b
O
Data bus output for FIFO-b. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode wth
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the lowand
high nibble transfer Slave Mode wth BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the lowand high nibble transfer
11
SOCS-b
O
Start Of Cell (FIFO-b). Output fromUtopiaFIFO. Active on first byte of data transfer SOCS deasserts
for all remaining byte transfers.
12
CLAVS-b
I
Cell Available (FIFO-b). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
13
-b
I/O
Enable (FIFO-b). Master Mode:
place on the current clock cycle. Slave Mode:
data nibble (Q0-3) on the output bus on the next read clock edge.
is an active lowoutput. When asserted, a data transfer wll take
is an input which causes the fifo port to update a
14, 16-20,
22-24
DATA-c
O
Data bus output for FIFO-c. Master Mode wth BNE HIGH: output is a 9-bit word. Master Mode wth
BNE LOW: data bus output is a data nibble (Q0-Q-3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the lowand
high nibble transfer Slave Mode wth BNE LOW: data bus output is a data nibble (Q1-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the lowand high nibble transfer
25
SOCS-c
O
Start Of Cell (FIFO-c). Output fromUtopiaFIFO. Active on first byte of data transfer SOCS deasserts
for all remaining byte transfers.
26
CLAVS-c
I
Cell Available (FIFO-c) CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
28
-c
I/O
Enable (FIFO-c). Master Mode:
place on the current clock cycle. Slave Mode:
data nibble (Q0-3) on the output bus on the next read clock edge.
is an active lowoutput. When asserted, a data transfer wll take
is an input which causes the fifo port to update a
29-32,
34-38
DATA-d
O
Data bus output for FIFO-d. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode wth
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the lowand
high nibble transfer Slave Mode wth BNE LOW; data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the lowand high nibble transfer
40
SOCS-d
O
Start Of Cell (FIFO-d). Output fromUtopiaFIFO. Active on first byte of data transfer SOCS deasserts
for all remaining byte transfers.
41
CLAVS-d
I
Cell Available (FIFO-d). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
42
-d
I/O
Enable (FIFO-d). Master Mode:
place on the current clock cycle. Slave Mode:
data nibble (Q0-3) on the output bus on the next read clock edge.
is an active lowoutput. When asserted, a data transfer wll take
is an input which causes the fifo port to update a
43
I
Input port write enable. Each data write requires
assertion.
44
CLAVR
O
Input port Cell space Available. Notifies the controlling agent the FIFO(s) selected by the address
bus can accept a complete cell.
46
SOCR
I
Input port Start of Cell. Assertion: first work is currently on bus.
47-53
Data 17-11/
P_CS 6-0
I
BSS low (18-Bit bus): Data bus input Data 11-Data 17
BSS high (9-bit bus): Input port for loading programmable registers.
3240 tbl 01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT77305 | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| IDT77911 | Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| IDT77914 | NICStAR⑩ Reference Design 155Mbps Network Interface Card NIC |
| IDT77915 | NICStAR⑩ Reference Design 155Mbps Network Interface Card NIC |
| IDT77916 | NICStAR Reference Design 25Mbps ATM Network Interface Card NIC with PCI interface and UTP3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V011L155DA8 | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V106L25TF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77V106-L25TFI | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET TRANSCEIVER, 64 Pin, Plastic, QFP |
| IDT77V252L155PG | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。