參數(shù)資料
型號(hào)： IDT79RV4700200DPG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 200 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208
文件頁(yè)數(shù)： 23/25頁(yè)
文件大?。?/td> 711K
代理商： IDT79RV4700200DPG
7 of 25
April 10, 2001
IDT79R4700
ValidOut* and ValidIn* are used by the RC4700 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4700 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
Non-overlapping System Interface
The RC4700 bus uses a non-overlapping system interface. This
means that only one processor request may be outstanding at a time
and that the request must be serviced by an external device before the
RC4700 issues another request. The RC4700 can issue read and write
requests to an external device, and an external device can issue read
and write requests to the RC4700.
For processor read transaction the RC4700 asserts ValidOut* and
simultaneously drives the address and read command on the SysAD
and SysCmd buses. If the system interface has RdRdy* asserted, then
the processor tristates its drivers and releases the system interface to
slave state by asserting Release*. The external device can then begin
sending the data.
Figure 5 on page 10 shows a processor block read request and the
external agent read response. The read latency is four cycles (ValidOut*
to ValidIn*), and the response data pattern is DDxxDD. Figure 6 on
page 10 shows a processor block write.
Write Reissue and Pipeline Write
The RC4700 implements additional write protocols that have been
designed to improve performance. This implementation doubles the
effective write bandwidth. The write re-issue has a high repeat rate of
two cycles per write. A write issues if WrRdy* is asserted two cycles
earlier and is still asserted at the issue cycle. If it is not still asserted, the
last write re-issues again. Pipelined writes have the same two cycle per
write repeat rate but can issue one additional write after WrRdy* de-
asserts. They still follow the issue rule as R4x00 mode for other writes.
External Requests
The RC4700 responds to requests issued by an external device. The
requests can take several forms. An external device may need to supply
data in response to an RC4700 read request or it may need to gain
control over the system interface bus to access other resources which
may be on that bus. It also may issue requests to the processor, such as
a request for the RC4700 to write to the RC4700 interrupt register. The
RC4700 supports Write, Null, and Read Response external requests.
Boot-Time Options
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
information to be kept in a low-cost serial EEPROM; alternatively, the
20-or-so bits could be generated by the system interface ASIC or a
simple PAL.
Immediately after the VCCOK signal is asserted, the processor reads a
bit stream of 256 bits to initialize all fundamental operational modes.
After initialization is complete, the processor continues to drive the serial
clock output, but no further initialization bits are read.
JTAG Interface
The RC4700 supports the JTAG interface pins, with the serial input
connected to serial output. Boundary scan is not supported.
Boot-Time Modes
The boot-time serial mode stream is defined in Table 3. Bit 0 is the
first bit presented to the processor when VCCOK is asserted; bit 255 is the
last.
Power Management1
CP0 is also used to control the power management for the RC4700.
This is the standby mode and can be used to reduce the power
consumption of the internal core of the CPU. Standby mode is entered
by executing the WAIT instruction with the SysAD bus idle and is exited
by an interrupt.
Standby Mode Operations
The RC4700 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
Entering Standby Mode
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, some of the input pin
clocks (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*), and the
output clocks—TClock[1:0], RClock[1:0] SyncOut, Modeclock and
MasterOut—will continue to run. If the conditions are not correct when
the WAIT instruction finishes the W pipe-stage (such as the SysAd bus
is not idle), the WAIT is treated as a NOP.
Once the CPU is in Standby Mode, any interrupt— including the
internally generated timer interrupt—will cause the CPU to exit Standby
Mode.
1. The R4700 implements advanced power management, to substantially
reduce the average power dissipation of the device. This operation is described
in the R4700 Microprocessor Hardware User’s Manual.
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