參數(shù)資料
型號： IDT82P2521BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 106/147頁
文件大小： 0K
描述： IC LIU E1 21+1CH SHORT 640-PBGA
標準包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
61
December 7, 2005
3.5.2
CLOCK OUTPUTS ON REFA/REFB
The outputs on REFA and REFB can be enabled or disabled, as
determined by the REFA_EN bit (b6, REFA) and the REFB_EN bit (b6,
REFB) respectively.
When the output is disabled, REFA/REFB is in High-Z state.
When the output is enabled, the output of REFA and REFB varies in
different operations. Refer to below for detailed description. Refer to
Figure-38 and Figure-39 for an overview of REFA and REFB output
options in normal operation.
3.5.2.1 REFA/REFB in Clock Recovery Mode
In this mode (default), the clock of REFA and REFB is derived from
the recovered clock of one of the 22 channels as selected by the
REFA[4:0] bits (b4~0,REFA) and REFB[4:0] bits (b4~0,REFB). Deter-
mined by the FS_BYPAS bit (b4, REFCF) a Frequency Synthesizer can
be enabled for REFA (refer to Section 3.5.2.2 Frequency Synthesizer for
REFA Clock Output). If the Frequency Synthesizer is disabled, REFA
will output the recovered 2.048 MHz clock depending on the line mode
of the selected channel. REFB output the recovered 2.048 MHz clock
depending on the line mode of the selected channel.
The recovered line clock can be output to REFA and REFB before or
after it passed the receive Jitter Attenuator (RJA) selected by the
JA_BYPAS bit (b6, REFCF).
3.5.2.2 Frequency Synthesizer for REFA Clock Output
For REFA a Frequency Synthesizer can be enabled or bypassed
(default) as selected by FS_BYPASS bit (b4, REFCF). The output
frequency is selected by the FREQ[2:0] bits (b2~0, REFCF). Frequen-
cies supported are 8 KHz, 64 KHz, 2.048 MHz, 4.096 MHz, 8.192 MHz,
19.44 MHz or 32.768 MHz.
3.5.2.3 Free Run Mode for REFA Clock Output
REFA can also be selected to provide a free running clock locked to
MCLK. To enable this mode the Frequency Synthesizer has to be
enabled by setting the FS_BYPAS bit (b4, REFCF) to ‘0’, and the FREE
bit (b3, REFCF) has to be set to ‘1’. REFA will provide a frequency
selected by the FREQ[2:0]1 bits (b2~0, REFCF) which is a free running
clock locked to MCLK.
3.5.2.4 REFA/REFB Driven by External CLKA/CLKB Input
In this mode, the clock of REFA and REFB is driven from an external
clock input of CLKA and CLKB respectively. CLKA and CLKB are
selected as an input source by setting REFA[4:0] bits (b4~0, REFA) and
REFB[4:0] bits (b4~0, REFB) to any value from ‘11101’ to ‘11111’.
CLKA and CLKB are an external E1 (2.048 MHz) Clock Input. The
CKA_E1 bit (b5, REFA) and CKB_E1 bit (b5, REFB) should be set to
match the input clock frequency.
Determined by the FS_BYPASS bit (b4, REFCF), a Frequency
Synthesizer can be enabled for REFA (refer to Section 3.5.2.2
Synthesizer is disabled, REFA and REFB will output the 2.048 MHz
clock.
3.5.2.5 REFA and REFB in Loss of Signal (LOS) or Loss of Clock
Condition
If the recovered clock of one of the 22 channels is selected as the
clock source for REFA and REFB (refer to Section 3.5.2.1 REFA/REFB
in Clock Recovery Mode) and Line LOS (LLOS) is detected in the corre-
sponding channel, the state of output on REFA and REFB can be
selected by the REFH bit (b5, REFCF). If REFH is set to ‘1’, REFA and
REFB will output a high level in case of LLOS. If REFH is set to ‘0’ and
LLOS is detected, REFA and REFB clock outputs will be locked to
MCLK while the selected clock frequency will remain unchanged.
LLOS condition is set when LLOS_S bit (b0, STAT0) is ‘1’. Refer to
Refer to Figure-40 for a detailed overview of REFA output in case of
LLOS. REFB output option is only determined by the REFH bit (b5,
REFCF) to be locked to MCLK or set to high level output.
If CLKA is selected as the clock source for REFA (refer to
there is no clock input on CLKA for more than 8 E1 clock cycles if E1
mode is selected (i.e. CKA_E1 bit (b5, REFA) is ‘1’), the state of the
REFA output is determined by the FS_BYPAS bit (b4, REFCF) and the
FREE bit (b3, REFCF). In case the Frequency Synthesizer is disabled
(i.e. FS_BYPAS bit (b4, REFCF) is ‘0’). REFA will output a high level. If
the Frequency Synthesizer is enabled and the FREE bit (b3, REFCF) is
set to ‘0’, REFA will output a high level. If the Frequency Synthesizer is
enabled and the FREE bit (b3, REFCF) is set to ‘1’, REFA will be locked
to MCLK.
Refer to Figure-41 for a detailed overview of REFA output in case of
loss of CLKA.
If CLKB is selected as the clock source for REFB (refer to section
there is no clock input on CLKB for more than 8 E1 clock cycles if E1
mode is selected (i.e. CKB_E1 bit (b5, REFB) is ‘1’), the output on REFB
is determined by the REFH bit (b5, REFCF). If REFH is set to ‘1’, REFB
will output a high level. If REFH is set to ‘0’, the REFB clock output will
be locked to MCLK.
1. ‘000’ and ‘011’ are reserved for FREQ[2:0] in this mode.
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