參數(shù)資料
型號： IDT82P2521BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 76/147頁
文件大?。?/td> 0K
描述： IC LIU E1 21+1CH SHORT 640-PBGA
標準包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
34
December 7, 2005
3.1.7
RECEIVER POWER DOWN
Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre-
sponding receiver.
In this way, the corresponding receive circuit is turned off and the
RTIPn/RRINGn pins are forced to High-Z state. The pins on receive
system interface (including RDn/RDPn, RDNn/RMFn, RCLKn/RMFn)
will be in High-Z state if the RHZ bit (b6, RCF0,...) is ‘1’ or in low level if
the RHZ bit (b6, RCF0,...) is ‘0’.
After clearing the R_OFF bit (b5, RCF0,...), it will take 1 ms for the
receiver to achieve steady state, i.e., to return to the previous configura-
tion and performance.
3.2
TRANSMIT PATH
3.2.1
TRANSMIT SYSTEM INTERFACE
The data from the system side is input to the device in three modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode and Dual
Rail RZ Format mode, as selected by the T_MD[1:0] bits (b1~0,
If data is input on TDn in NRZ format and a 2.048 MHz clock is input
on TCLKn, the transmit system interface is in Single Rail NRZ Format
mode. In this mode, the data is encoded and sampled on the active
edge of TCLKn. TMFn is updated on the active edge of TCLKn and can
be selected to indicate PRBS/ARB, SAIS, TOC, TLOS or SEXZ. Refer to
Section 3.4.7.2 TMFn Indication for the description of TMFn.
If data is input on TDPn and TDNn in NRZ format and a 2.048 MHz
clock is input on TCLKn, the transmit system interface is in Dual Rail
NRZ Format mode. In this mode, the data is pre-encoded and sampled
on the active edge of TCLKn.
If data is input on TDPn and TDNn in RZ format and no transmit
clock is input, the transmit system interface is in Dual Rail RZ Format
mode. In this mode, the data is pre-encoded. TMFn can be selected to
indicate PRBS/ARB, SAIS, TOC, TLOS, SEXZ, SBPV, SEXZ + SBPV or
SLOS. Refer to Section 3.4.7.2 TMFn Indication for the description of
TMFn. The Tx Clock Recovery block is used to recover the clock signal
from the data input on TDPn and TDNn. Refer to Section 3.2.2 Tx Clock
Table-3 summarizes the multiplex pin used in different transmit
system interface.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P2521BHBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit
IDT82P2521BHG 功能描述:IC LIU E1 21+1CH SHORT 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2521BHGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit
IDT82P2808 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8(+1) Channel High-Density T1/E1/J1 Line Interface Unit
IDT82P2808BB 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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