參數(shù)資料
型號(hào)： IDT82P2521BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 145/147頁
文件大小： 0K
描述： IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2521BHG
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Programming Information
97
December 7, 2005
ERR - Error Detection & Insertion Control Register
1 - 0
TDLOS[1:0]
These bits select the period. When the amplitude of the data is less than a certain voltage for the period, TLOS is declared. The
voltage is determined by the TALOS bits (b3~2, LOS,...).
00: 16-pulse.
01: 32-pulse. (default)
1X: 64-pulse.
Address: 00EH, 04EH, 08EH, 0CEH, 10EH, 14EH, 18EH, 1CEH, (CH1~CH8)
20EH, 24EH, 28EH, 2CEH, 30EH, 34EH, 38EH, 3CEH, (CH9~CH16)
40EH, 44EH, 48EH, 4CEH, 50EH, (CH17~CH21)
7CEH (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7
EXZ_DEF
This bit selects the EXZ definition standard.
0: ANSI. (default)
1: FCC.
6
BPV_INS
This bit controls whether to insert a bipolar violation (BPV) to the transmit path.
Writing ‘1’ to this bit will insert a BPV on the next available mark in the data stream to be transmitted.
This bit is cleared once the BPV insertion is completed.
5
ERR_INS
This bit controls whether to insert a single bit error to the generated PRBS/ARB pattern.
A transition from ‘0’ to ‘1’ on this bit will insert a single bit error to the generated PRBS/ARB pattern.
This bit is cleared once the single bit error insertion is completed.
4 - 2
CNT_SEL[2:0] These bits select what kind of error to be counted by the internal Error Counter.
000: Disable. (default)
001: LBPV.
010: LEXZ.
011: LBPV + LEXZ.
100: SBPV.
101: SEXZ.
110: SBPV + SEXZ.
111: PRBS/ARB error.
1
CNT_MD
This bit determines whether the ERRCH & ERRCL registers are updated automatically or manually.
0: Manually by setting the CNT_STOP bit (b0, ERR,...). (default)
1: Every-one second automatically.
0
CNT_STOP
This bit is valid only when the CNT_MD bit (b1, ERR,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the ERRCH & ERRCL registers.
This bit must be cleared before the next round.
7
654321
0
EXZ_DEF
BPV_INS
ERR_INS
CNT_SEL2
CNT_SEL1
CNT_SEL0
CNT_MD
CNT_STOP
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