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參數(shù)資料
| 型號： | IDT82P2816BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/146頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 16+1CH 416-PBGA |
| 標準包裝： | 5 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 416-BGA |
| 供應商設備封裝： | 416-PBGA（27x27） |
| 包裝： | 托盤 |
| 包括： | 缺陷和警報檢測，驅(qū)動器過流檢測和保護，LLOS 檢測，PRBSARB / IB 檢測和生成 |
| 其它名稱： | 82P2816BB |
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IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Applications
11
February 6, 2009
APPLICATIONS
SDH/SONET multiplexers
Central office or PBX (Private Branch Exchange)
Digital access cross connects
Remote wireless modules
Microwave transmission systems
DESCRIPTION
The IDT82P2816 is a 16+1 channels high-density T1/E1/J1 short
haul Line Interface Unit. Each channel of the IDT82P2816 can be inde-
pendently configured. The configuration is performed through a Serial or
Parallel Intel/Motorola Non-Multiplexed /Multiplexed microprocessor
interface.
In the receive path, through a Single Ended or Differential line inter-
face, the received signal is processed by an adaptive Equalizer and then
sent to a Slicer. Clock and data are recovered from the digital pulses
output from the Slicer. After passing through an enabled or disabled
Receive Jitter Attenuator, the recovered data is decoded using B8ZS/
AMI/HDB3 line code rule in Single Rail NRZ Format mode and output to
the system, or output to the system without decoding in Dual Rail NRZ
Format mode and Dual Rail RZ Format mode.
In the transmit path, the data to be transmitted is input on TDn in
Single Rail NRZ Format mode or TDPn/TDNn in Dual Rail NRZ Format
mode and Dual Rail RZ Format mode, and is sampled by a transmit
reference clock. The clock can be supplied externally from TCLKn or
recovered from the input transmit data by an internal Clock Recovery. A
selectable JA in Tx path is used to de-jitter gapped clocks. To meet T1/
E1/J1 waveform standards, five preset T1 templates and two E1
templates, as well as an arbitrary waveform generator are provided. The
data through the Waveform Shaper, the Line Driver and the Tx Trans-
mitter is output on TTIPn and TRINGn.
Alarms (including LOS, AIS) and defects (including BPV, EXZ) are
detected in both receive line side and transmit system side. AIS alarm,
PRBS, ARB and IB patterns can be generated /detected in receive /
transmit direction for testing purpose. Analog Loopback, Digital Loop-
back and Remote Loopback are all integrated for diagnostics.
Channel 0 is a special channel. Besides normal operation as the
other 16 channels, channel 0 also supports G.772 Monitoring and Jitter
Measurement per ITU O.171.
A line monitor function per T1.102 is available to provide a Non-Intru-
sive Monitoring of channels of other devices.
JTAG per IEEE 1149.1 is also supported by the IDT82P2816.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2816BBG | 功能描述:IC LINE INTERFACE UNIT 416-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| IDT82P2821 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2821BH | 功能描述:IC LIU T1/J1/E1 21+1CH 640-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| IDT82P2821BHG | 功能描述:IC LINE INTERFACE UNIT 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| IDT82P2828 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
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