IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
31
October 7, 2003
3.8.2.1.2
CRC Multi-Frame
The CRC Multi-Frame is provided to enhance the ability of verifying
the data stream. The structure of TS0 of the CRC Multi-Frame is illus-
trated in Table 18.
A CRC Multi-Frame consists of 16 continuous Basic Frames (No. 0
– 15) which are numbered from a Basic Frame with FAS. Each CRC
Multi-Frame can be divided into two Sub Multi-Frames (SMF I & SMF II).
The first bit of TS0 of each frame is called the International (Si) bit.
The Si bit in each even frame is the CRC bit. Thus, there are C1, C2,
C3, C4 in each SMF. The C1 is the most significant bit, while the C4 is
the least significant bit. The Si bit in the first six odd frames is the CRC
Multi-Frame alignment pattern. Its pattern is ‘001011’. The Si bit in
Frame 13 and Frame 15 are E1 and E2 bits. The value of the E bits can
indicate the Far End Block Errors (FEBE).
After the Basic Frame has been synchronized, the Frame Proces-
sor initiates an 8 and a 400 ms timer to check the CRC Multi-Frame
alignment signal if the CRCEN bit is ‘1’. The CRC Multi-Frame synchro-
nization is declared with a ‘0’ in the OOCMFV bit only if at least two CRC
Multi-Frame alignment patterns are found within 8 ms, with the interval
time of each pattern being a multiple of 2 ms. Then if the received CRC
Multi-Frame alignment signal does not meet its pattern, it will be indi-
cated by the CMFERI bit.
If the 2 CRC Multi-Frame alignment patterns can not be found
within 8ms with the interval time being a multiple of 2 ms, an offline
search for the Basic Frame alignment pattern will start which is indicated
in the OOOFV bit. The process is the same as shown in Figure 10. This
offline operation searches in parallel with the pre-found Basic Frame
synchronization searching process. After the new Basic Frame synchro-
nization is found by this offline search, the 8 ms timer is restarted to
check whether the two CRC Multi-Frame alignment patterns are found
within 8 ms, with the interval time of each pattern being a multiple of 2
ms again. If the condition can not be met, the procedure will go on until
the 400 ms timer ends. If the condition still can not be met at that time
and the Basic Frame is still synchronized, the device declares by the
C2NCIWV bit to run under the CRC to non-CRC interworking process. In
this process, the CRC Multi-Frame alignment pattern can still be
searched if the C2NCIWCK bit is logic 1.
Table 18: The Structure Of TS0 In CRC Multi-Frame
SMF
Basic Frame
No. / Type
the Eight Bits in Timeslot 0
1 (Si bit)
2
3
4
5
6
7
8
CRC-4
Multi-Frame
SMF I
0 / FAS
1 / NFAS
2 / FAS
3 / NFAS
4 / FAS
5 / NFAS
6 / FAS
7 / NFAS
8 / FAS
9 / NFAS
10 / FAS
11 / NFAS
12 / FAS
13 / NFAS
14 / FAS
15 / NFAS
C1
0
C2
0
C3
1
C4
0
C1
1
C2
1
C3
E1
C4
E2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
1
1
0
1
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
SMF II