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參數(shù)資料
| 型號： | IDT82V1068 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | Codec |
| 英文描述： | OCTAL PROGRAMMABLE PCM CODEC |
| 中文描述： | 八路可編程PCM編解碼器 |
| 文件頁數(shù)： | 44/375頁 |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82V1068 |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
33
October 7, 2003
10. NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of
a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network
Terminal CRC Error event is generated. This error event is captured by
the TCRCEI bit and is forwarded to the Performance Monitor.
Various errors will lead to out of synchronization:
3.8.2.2.1
Out Of Basic Frame Synchronization
If there is one or more bit errors in a FAS pattern, a FAS pattern
error will occur. If the NFAS bit position is received as zero, a NFAS error
will occur. Determined by the BIT2C bit, if this bit is ‘0’, 3 consecutive
FAS pattern errors lead to out of Basic frame synchronization; if this bit
is ‘1’, 3 consecutive FAS pattern errors or 3 consecutive NFAS errors
lead to out of Basic frame synchronization. Then if the REFEN bit is ‘1’,
the Frame Processor will start to search for synchronization again. Addi-
tionally, Excessive CRC-4 Error also leads to out of Basic frame syn-
chronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for syn-
chronization again. If the REFEN bit is ‘0’, no error can lead to reframe
except for manually setting. The manual reframe searches from Basic
frame and is executed by a transition from ‘0’ to ‘1’ on the REFR bit. Dur-
ing out of Basic frame synchronization state, the FAS/NFAS Bit/Pattern
Error detection is suspended.
Once resynchronized, if the new-found Basic frame alignment pat-
tern position differs from the previous one, the change of frame align-
ment event is generated. This event is captured by the COFAI bit and is
forwarded to the Performance Monitor.
3.8.2.2.2
Out Of CRC Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CRC Multi-Frame synchronization. During out of CRC
Multi-Frame synchronization state, the FAS/NFAS Bit/Pattern Error
detection, CRC Multi-Frame Alignment Pattern Error detection, CRC-4
Error detection, Excessive CRC-4 Error detection, Far End Block Error
detection, Continuous RAI & FEBE Error detection, Continuous FEBE
Error detection, NT CRC Error detection and NT FEBE Error detection
are suspended.
3.8.2.2.3
Out Of CAS Signaling Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CAS Signaling Multi-Frame synchronization.
In addition, determined by the SMFASC bit and the TS16C bit, if the
CAS Signaling Multi-Frame Alignment Pattern Error occurs or all the
contents in TS16 are zeros, it is out of CAS Signaling Multi-Frame syn-
chronization. Then no matter what the value in the REFEN bit is, the
Frame Processor will search for the CAS Signaling Multi-Frame syn-
chronization again only if the Basic frame is in synchronization. During
out of CAS Signaling Multi-Frame synchronization state, the CAS Sig-
naling Multi-Frame Alignment Pattern Error detection is suspended.
3.8.2.3
Overhead Extraction
3.8.2.3.1
International Bit Extraction
The International bits (Si bits, refer to Table 18) are extracted to the
Si[0:1] bits in the TS0 International / National register. The Si[0:1] bits in
the TS0 International / National register are updated on the boundary of
the associated FAS/NFAS frame and are held during out of Basic frame
state.
3.8.2.3.2
Remote Alarm Indication Bit Extraction
The Remote Alarm Indication bit (A bit, refer to Table 18) is
extracted to the A bit in the TS0 International / National register. The A
bit in the TS0 International / National register is updated on the bound-
ary of the associated NFAS frame and is held during out of Basic frame
state.
3.8.2.3.3
National Bit Extraction
The National bits (Sa bits, refer to Table 18) are extracted to the
Sa[4:8] bits in the TS0 International / National register. The Sa[4:8] bits
in the TS0 International / National register are updated on the boundary
of the associated NFAS frame and are held during out of Basic frame.
3.8.2.3.4
National Bit Codeword Extraction
The five sets of the National Bit codewords (Sa4[1:4] to Sa8[1:4] in
the CRC Sub Multi-Frame, refer to Table 18) are extracted to the corre-
sponding SaX Codeword register. Here the ‘X’ is from 4 through 8. The
National Bit codeword extraction will be set to de-bounce if the SaDEB
bit is set to ‘1’. Thus, the SaX Codeword registers are updated if the
received National Bit codeword is the same for 2 consecutive CRC Sub
Multi-Frames. Whether de-bounced or not, a change indication will be
set in the SaXI bit (‘X’ is from 4 through 8) if the corresponding codeword
in the SaX Codeword register differs from the previous one.
The value in the SaX Codeword registers is held during out of CRC
Multi-Frame synchronization state.
3.8.2.3.5
Extra Bit Extraction
The Extra bits (X bits, refer to Figure 11) are extracted to the X[0:2]
bits in the TS16 Spare register. The X[0:2] bits in the TS16 Spare regis-
ter are updated at the first bit of the next CAS Signaling Multi-Frame and
are held during out of CAS Signaling Multi-Frame state.
3.8.2.3.6
Extraction
The Remote Signaling Multi-Frame Alarm Indication bit (Y bit, refer
to Figure 11) are extracted to the Y bit in the TS16 Spare register. The Y
bit in the TS16 Spare register is updated at the first bit of the next CAS
Signaling Multi-Frame and is held during out of CAS Signaling Multi-
Frame state.
Remote Signaling Multi-Frame Alarm Indication Bit
3.8.2.3.7
Sa6 Code Detection Per ETS 300 233
When Basic frame is synchronized, any 12 consecutive Sa6 bits
(MSB is the first received bit) are compared with 0x888, 0xAAA, 0xCCC,
0xEEE and 0xFFF. When CRC Multi-Frame is synchronized, any 3 con-
secutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are com-
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| IDT82V1068PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
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