參數(shù)資料
型號: IDT82V2048DAG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 18/62頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 144-TQFP
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
包裝: 托盤
其它名稱: 82V2048DAG
25
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
are configured properly. The required sequence for configuring the
Inband Loopback Generator is: First, set registers e-LBAC and e-LBDC,
followed by register e-LBCF. Then, to select the Inband Loopback
generator set registers e-LBGS and then e-LBGE.
The Inband Loopback Detection and the Inband Loopback Genera-
tion can not be used simultaneously.
Example: 5-bit Loop-up/Loop-down Detection (w/o interrupts):
(see note in register description for e-LBAC)
Loop-up code: 11000
Loop-down code: 11100
Set (in this order)
e-LBAC (0x09) = 0xC6 (11000110)
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x30
Example: 5-bit Loop-up/Loop-down Activation on Channel 1 (w/o
interrupts):
Loop-up code: 11000
Loop-down code: 11100
Set (in this order)
e-LBAC (0x09) = 0xC6 (11000110)
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x00
e-LBGS (0x0E) = 0x00
e-LBGE (0x0F) = 0x02
2.18 HOST INTERFACE
The host interface provides access to read and write the registers in
the device. The interface consists of serial host interface and parallel
host interface. By pulling pin MODE2 to VDDIO/2 or high, the device can
be set to work in serial mode and in parallel mode respectively.
2.18.1 PARALLEL HOST INTERFACE
The interface is compatible with Motorola and Intel host. Pins
MODE1 and MODE0 are used to select the operating mode of the
parallel host interface. When pin MODE1 is pulled low, the host uses
separate address bus and data bus. When high, multiplexed address/
data bus is used. When pin MODE0 is pulled low, the parallel host inter-
face is configured for Motorola compatible hosts. When pin MODE0 is
pulled high, the parallel host interface is configured for Intel compatible
hosts. See Table-1 Pin Description for more details. The host interface
pins in each operation mode is tabulated in Table-14:
Figure-22 Serial Host Mode Timing
2.18.2 SERIAL HOST INTERFACE
By pulling pin MODE2 to VDDIO/2, the device operates in the serial
host Mode. In this mode, the registers are accessible through a 16-bit
word which contains an 8-bit command/address byte (bit R/W and 5-
address-bit A1~A5, A6 and A7 bits are ignored) and a subsequent 8-bit
data byte (D7~D0), as shown in Figure-22. When bit R/W is set to ‘1’,
data is read out from pin SDO. When bit R/W is set to ‘0’, data on pin
SDI is written into the register whose address is indicated by address
Table-14 Parallel Host Interface Pins
MODE[2:0]
Host Interface
Generic Control, Data and Output Pin
100
Non-multiplexed Motorola interface
CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT
101
Non-multiplexed Intel interface
CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT
110
Multiplexed Motorola interface
CS, ACK, DS, R/W, AS, AD[7:0], INT
111
Multiplexed Intel interface
CS, RDY, WR, RD, ALE, AD[7:0], INT
A1
A3
A2
A4 A5 A6
D0 D1 D2 D3 D4 D5 D6 D7
R/W
D0 D1 D2 D3 D4 D5 D6 D7
A7
Input Data Byte
Address/Command Byte
High Impedance
Driven while R/W=1
SDI
SDO
SCLK
CS
1
22
1. While R/W=1, read from IDT82V2048; While R/W=0, write to IDT82V2048.
2. Ignored.
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