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參數(shù)資料
| 型號： | IDT82V2048DAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 39/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標準包裝： | 30 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048DAG |
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.3
TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure-
26 shows its state diagram A description of each state follows. Note that
the figure contains two main branches to access either the data or
instruction registers. The value shown next to each state transition in
this figure states the value present at TMS at each rising edge of TCK.
Refer to Table-22 for details of the state description.
Table-22 TAP Controller State Description
State
Description
Test Logic Reset
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register
with the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5
rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically enters this state at power-up.
Run-Test/Idle
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The
instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller
moves to the Select-DR state.
Select-DR-Scan
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction
retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR
state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller
moves to the Select-IR-Scan state.
Capture-DR
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction
does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in
this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
Shift-DR
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward
its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
Exit1-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR
state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-DR
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI
and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test
sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller
moves to the Exit2-DR state.
Exit2-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-DR
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into
the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes
only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruc-
tion does not change during this state.
Select-IR-Scan
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and
a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction reg-
ister is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction
does not change during this state.
Capture-IR
In this controller state, the shift register contained in the instruction register loads a fixed value of ‘100’ on the rising edge of TCK. This sup-
ports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruc-
tion does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-
IR state if TMS is held high, or the Shift-IR state if TMS is held low.
Shift-IR
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its
serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
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相關代理商/技術參數(shù) |
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|---|---|
| IDT82V2048E | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2048EBB | 功能描述:IC LIU T1/E1 8CH SHORT 208-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048EBBG | 功能描述:IC LINE INTERFACE UNIT 208-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:2,500 系列:- 類型:驅動器 驅動器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC N 包裝:帶卷 (TR) |
| IDT82V2048EDR | 功能描述:IC LIU T1/E1 8CH SHORT 208-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL T1/E1 SHORT HAUL ANALOG FRONT END |
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