參數(shù)資料
型號: IDT82V2048LBBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/48頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 160-BGA
標(biāo)準(zhǔn)包裝: 14
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 160-BGA
供應(yīng)商設(shè)備封裝: 160-PBGA(15x15)
包裝: 托盤
其它名稱: 82V2048LBBG
16
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
2.10 LINE PROTECTION
In transmit side, the Schottky diodes D1~D4 are required to protect
the line driver and improve the design robustness. In receive side, the
series resistors of 1 k are used to protect the receiver against current
surges coupled in the device. The series resistors do not affect the
receiver sensitivity, since the receiver impedance is as high as 120 k
typically.
2.11 HITLESS PROTECTION SWITCHING (HPS)
The IDT82V2048L transceivers include an output driver with high
impedance feature for T1/E1 redundancy applications. This feature
reduces the cost of redundancy protection by eliminating external relays.
Details of HPS are described in relative Application Note.
2.12 TRANSMIT ALL ONES (TAOS)
In hardware mode, the TAOS mode is set by pulling pin TCLKn high
for more than 16 MCLK cycles. In host mode, TAOS mode is set by
programming register TAO. In addition, automatic TAOS signals are
inserted by setting register ATAO when Loss of Signal occurs. Note that
the TAOS generator adopts MCLK as a timing reference. In order to
assure that the output frequency is within specified limits, MCLK must
have the applicable stability.
Figure-8 TAOS Data Path
2.13 G.772 MONITORING
The eight channels of IDT82V2048L can all be configured to work as
regular transceivers. In applications using only seven channels (chan-
nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the
other channels’ inputs or outputs on the line side. The monitoring is non-
intrusive per ITU-T G.772. Figure-9 shows the Monitoring Principle. The
receiver path or transmitter path to be monitored is configured by pin
MC[3:0] in hardware mode or by PMON in host mode.
The signal which is monitored can be observed digitally at the output
pin RC0, RDP0 and RDN0. LOS detector is still in use in channel 0 for
the monitored signal.
In monitoring mode, a clock and data recovery circuit can be enabled
for Remote Loopback operation. In Remote Loopback operation, the
signal which is being monitored will be also output on TTIP0 and
TRING0 pins. The output signal can then be connected to a standard
test equipment for non-intrusive monitoring. RC0 pin will also output the
recovered clock (DPLL).
The remote loopback is only available in host mode operation.
To enable the remote loopback, bit 0 in register RL0 has to be set,
and bit 0 in register e-AFE has to be cleared. The register setting are:
register RL0 set ‘01’H, register e-AFE set ‘FE’H.
For normal operation register RL0 has to be set ‘00H’ and register e-
AFE has to be set ‘FFH’.
Slicer
Peak
Detector
Line
Driver
Waveform
Shaper
LOS
Detector
One of Eight Identical Channels
RTIPn
RRINGn
TTIPn
TRINGn
LOSn
RCn
RDPn
RDNn
TCLKn
TDNn
TDPn
Transmit
All Ones
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