Figure-9 Monitoring Principle 2.14 SOFTWARE RESET
參數(shù)資料
型號: IDT82V2048LBBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/48頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 160-BGA
標(biāo)準(zhǔn)包裝: 14
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 160-BGA
供應(yīng)商設(shè)備封裝: 160-PBGA(15x15)
包裝: 托盤
其它名稱: 82V2048LBBG
17
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Figure-9 Monitoring Principle
2.14 SOFTWARE RESET
Writing register RS will cause software reset by initiating about 1 s
reset cycle. This operation set all the registers to their default value.
2.15 POWER ON RESET
During power up, an internal reset signal sets all the registers to
default values. The power-on reset takes at least 10 s, starting from
when the power supply exceeds 2/3 VDDA.
2.16 POWER DOWN
Each transmit channel will be powered down by pulling pin TCLKn
low for more than 64 MCLK cycles (if MCLK is available) or about 30 s
(if MCLK is not available). In host mode, each transmit channel will also
be powered down by setting bit TPDNn in register e-TPDN to ‘1’.
All the receivers will be powered down when MCLK is low. When
MCLK is clocked or high, setting bit RPDNn in register e-RPDN to ‘1’ will
configure the corresponding receiver to be powered down.
2.17 INTERFACE WITH 5 V LOGIC
The IDT82V2048L can interface directly with 5 V TTL family devices.
The internal input pads are tolerant to 5 V output from TTL and CMOS
family devices.
Slicer
Peak
Detector
Line
Driver
Waveform
Shaper
LOS
Detector
Channel N ( 7 > N > 1 )
RTIPn
RRINGn
TTIPn
TRINGn
LOSn
RCn
RDPn
RDNn
TCLKn
TDNn
TDPn
G.772
Monitor
Transmit
All Ones
Slicer
Peak
Detector
Line
Driver
Waveform
Shaper
LOS
Detector
Channel 0
LOS0
RC0
RDP0
RDN0
TCLK0
TDN0
TDP0
Transmit
All Ones
RTIP0
RRING0
TTIP0
TRING0
Remote
Loopback
CDR
Remote
Loopback
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