參數(shù)資料
型號: IDT82V2048SDAG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 19/62頁
文件大小: 0K
描述: IC LIU T1/E1 8CH SHORT 144-TQFP
標(biāo)準(zhǔn)包裝: 5,000
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
包裝: 托盤
其它名稱: 82V2048SDAG
26
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
2.19 INTERRUPT HANDLING
2.19.1 INTERRUPT SOURCES
There are four kinds of interrupt sources:
1. Status change in register LOS. The analog/digital loss of signal
detector continuously monitors the received signal to update the
specific bit in register LOS which indicates presence or absence
of a LOS condition.
2. Status change in register DF. The automatic power driver circuit
continuously monitors the output drivers signal to update the
specific bit in register DFM which indicates presence or absence
of an output driver short circuit condition.
3. Status change in register AIS. The AIS detector monitors the
received signal to update the specific bit in register AIS which
indicates presence or absence of a AIS condition.
4. Status change in register e-LBS. The IBLC detector monitors
the inband loopback activation or deactivation code in received
signal to update the specific bit in register e-LBS which indicates
presence or absence of an inband loopback condition.
Figure-22 Interrupt Service Routine
2.19.2 INTERRUPT ENABLE
The IDT82V2048S provides a latched interrupt output (INT) and the
four kinds of interrupts are all reported by this pin. When the Interrupt
Mask register (LOSM, DFM, AISM and e-LBM) is set to ‘1’, the Interrupt
Status register (LOSI, DFI, AISI and e-LBI) is enabled respectively.
Whenever there is a transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corresponding
status register, the Interrupt Status register will change into ‘1’, which
means an interrupt occurs, and there will be a high to low transition on
INT pin. An external pull-up resistor of approximately 10 k
is required
to support the wire-OR operation of INT. When any of the four Interrupt
Mask registers is set to ‘0’ (the power-on default value is ‘0’), the corre-
sponding Interrupt Status register is disabled and the transition on status
register is ignored.
2.19.3 INTERRUPT CLEARING
When an interrupt occurs, the Interrupt Status registers: LOSI, DFI,
AISI and e-LBI, are read to identify the interrupt source. These registers
will be cleared to ‘0’ after the corresponding status registers: LOS, DF,
AIS and e-LBS are read. The Status registers will be cleared once the
corresponding conditions are met.
Pin INT is pulled high when there is no pending interrupt left. The
interrupt handling in the interrupt service routine is showed in Figure-22.
2.20 G.772 MONITORING
The eight channels of IDT82V2048S can all be configured to work as
regular transceivers. In applications using only seven channels (chan-
nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the
other channels’ inputs or outputs on the line side. The monitoring is non-
intrusive per ITU-T G.772. Figure-23 shows the Monitoring Principle.
The receiver path or transmitter path to be monitored is configured by
pins MC[3:0] in hardware mode or by register PMON in host mode.
The monitored signal goes through the clock and data recovery
circuit of channel 0. The monitored clock can output on RCLK0 which
can be used as a timing interfaces derived from E1 signal. The moni-
tored data can be observed digitally at the output pins RCLK0, RD0/
RDP0 and RDN0. LOS detector is still in use in channel 0 for the moni-
tored signal.
In monitoring mode, channel 0 can be configured in Remote Loop-
back. The signal which is being monitored will output on TTIP0 and
TRING0. The output signal can then be connected to a standard test
equipment with an E1 electrical interface for non-intrusive monitoring.
Service the Interrupt
Read Interrupt Status Register
Read Corresponding Status
Register
Interrupt Allowed
Interrupt Condition
Exist?
Yes
No
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