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參數(shù)資料
| 型號： | IDT82V2048SDAG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048SDAG |
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12
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED OPTION
INDUSTRIAL TEMPERATURE RANGES
2
FUNCTIONAL DESCRIPTION
2.1
OVERVIEW
The IDT82V2048S is a fully integrated octal short-haul line interface
unit, which contains eight transmit and receive channels for use in either
T1 or E1 applications. The receiver performs clock and data recovery.
As an option, the raw sliced data (no retiming) can be output to the
system. Transmit equalization is implemented with low-impedance
output drivers that provide shaped waveforms to the transformer, guar-
anteeing template conformance. A selectable jitter attenuator may be
placed in the receive path or the transmit path. Moreover, multiple
testing functions, such as error detection, loopback and JTAG boundary
scan are also provided. The device is optimized for flexible software
control through a serial or parallel host mode interface. Hardware control
is also available. Figure-1 on page 1 shows one of the eight identical
channels operation.
2.2
T1/E1 MODE SELECTION
T1/E1 mode selection configures the device globally. In Hardware
Mode, the template selection pins TS[2:0], determine whether the opera-
tion mode is T1 or E1 (see Table-9 on page 19). In Host Mode, the
register TS determines whether the operation mode is T1 or E1.
2.2.1
LINE INTERFACE
The device supports two line interfaces: differential and single ended.
A differential receive termination on RTIPn and RRINGn is supported in
Host mode and Hardware mode by default. A Single Ended receive
termination on RTIPn is supported in Host mode only. By default, Differ-
ential receive termination is enabled. To enable Single Ended receive
termination, bit SRX in register e-SRX has to be set. See 2.4.1 Single
2.2.2
SYSTEM INTERFACE
The system interface of each channel can be configured to operate
in different modes:
1. Single rail interface with clock recovery.
2. Dual rail interface with clock recovery.
3. Dual rail interface with data recovery (that is, with raw data
slicing only and without clock recovery).
Each signal pin on system side has multiple functions depending on
which operation mode the device is in.
The Dual Rail interface consists of TDPn1, TDNn, TCLKn, RDPn,
RDNn and RCLKn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface; data received on RTIPn and
RRINGn in differential receive termination or received on RTIPn in
Single Ended receive termination at the line interface are transferred to
RDPn and RDNn while the recovered clock extracting from the received
data stream outputs on RCLKn. In Dual Rail operation, the clock/data
recovery mode is selectable. Dual Rail interface with clock recovery
shown in Figure-4 is a default configuration mode. Dual Rail interface
with data recovery is shown in Figure-5. Pin RDPn and RDNn, are raw
RZ slice outputs and internally connected to an EXOR which is fed to the
RCLKn output for external clock recovery applications.
In Single Rail mode, data transmitted from TDn appears on TTIPn
and TRINGn at the line interface. Data received on RTIPn and RRINGn
in differential receive termination or received on RTIPn in Single Ended
receive termination at the line interface appears on RDn while the recov-
ered clock extracting from the received data stream outputs on RCLKn.
When the device is in single rail interface, the selectable AMI or B8ZS/
HDB3 line encoder/decoder is available and any code violation in the
received data will be indicated at the CVn pin. The Single Rail mode has
2 sub-modes: Single Rail Mode 1 and Single Rail Mode 2. Single Rail
Mode 1, whose interface is composed of TDn, TCLKn, RDn, CVn and
RCLKn, is realized by pulling pin TDNn high for more than 16 consecu-
tive TCLK cycles. Single Rail Mode 2, whose interface is composed of
TDn, TCLKn, RDn, CVn, RCLKn and BPVIn, is realized by setting bit
CRS in register e-CRS2 and bit SING in register e-SING. The difference
between them is that, in the latter mode bipolar violation can be inserted
via pin BPVIn if AMI line code is selected.
The configuration of the Hardware Mode System Interface is summa-
rized in Table-2. The configuration of the Host Mode System Interface is
summarized in Table-3.
1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels.
2. The first letter ‘e-’ indicates expanded register.
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| IDT82V2051E | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2051EPP | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPP8 | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPPG | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2051EPPG8 | 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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