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| 型號(hào)： | IDT82V2081PPG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 15/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 1CH 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 80 |
| 類(lèi)型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 800-2347 82V2081PPG IDT82V2081PPG-ND |
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22
INDUSTRIAL
TEMPERATURE RANGES
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
In hardware control mode, TERM, PULS[3:0] pins can be used to select
impedance matching for both receiver and transmitter. If TERM pin is low,
external impedance network will be used for impedance matching. If TERM
pin is high, internal impedance will be used for impedance matching and
PULS[3:0] pins can be set to select the specific internal impedance. Refer
to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.2
LINE MONITOR
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
ingonchannelslocatedinotherchipscanbeperformedbytappingthemon-
itored channel through a high impedance bridging circuit. Refer to Figure-
9 and Figure-11.
After a high resistance bridging circuit, the signal arriving at the RTIP/
RRING is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0CH). For normal operation, the Monitor
Gain should be set to 0 dB.
In hardware control mode, MONT pin can be used to set the Monitor
Gain. When MONT pin is low, the Monitor Gain is 0 dB. When MONT pin
is high, the Monitor Gain is 26 dB. Refer to 5 HARDWARE CONTROL PIN
SUMMARY for details.
Figure-9 Monitoring Receive Line in Another Chip
Figure-10 Monitor Transmit Line in Another Chip
3.4.3
ADAPTIVE EQUALIZER
The adaptive equalizer can remove most of the signal distortion due to
intersymbol interference caused by cable attenuation. It can be enabled or
disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0BH).
When the adaptive equalizer is out of range, EQ_S bit (STAT0, 17H) will
be set to ‘1’ to indicate the status of equalizer. If EQ_IES bit (INTES, 16H)
is set to ‘1’, any changes of EQ_S bit will generate an interrupt and EQ_IS
bit (INTS0, 19H) will be set to ‘1’ if it is not masked. If EQ_IES is set to ‘0’,
only the ‘0’ to ‘1’ transition of the EQ_S bit will generate an interrupt and
EQ_IS bit will be set to ‘1’ if it is not masked. The EQ_IS bit will be reset after
being read.
The Amplitude/wave shape detector keeps on measuring the ampli-
tude/waveshapeoftheincomingsignalsduringanobservationperiod.This
observation period can be 32, 64, 128 or 256 symbol periods, as selected
by UPDW[1:0] bits (RCF2, 0CH). A shorter observation period allows
quicker responses to pulse amplitude variation while a longer observation
period can minimize the possible overshoots. The default observation
period is 128 symbol periods.
Based on the observed peak value for a period, the equalizer will be
adjusted to achieve a normalized signal. LATT[4:0] bits (STAT1, 18H) indi-
cate the signal attenuation introduced by the cable in approximately 2 dB
per step.
3.4.4
RECEIVE SENSITIVITY
For short haul application, the Receive Sensitivity for both E1 and T1/
J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for
E1 and -36 dB for T1/J1.
When the chip is configured by hardware, the short haul or long haul
operating mode can be selected by setting EQ pin. For short haul mode,
the Receive Sensitivity for both E1 and T1/J1 is -10 dB. For long haul mode,
thereceivesensitivityis-43dBforE1and-36dBforT1/J1.Referto5HARD-
WARE CONTROL PIN SUMMARY for details.
3.4.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be40%,50%,60%or70%,asselectedbytheSLICE[1:0]bits(RCF2,0CH).
The output of the Data Slicer is forwarded to the CDR (Clock & Data Recov-
ery) unit or to the RDP/RDN pins directly if the CDR is disabled.
3.4.6
CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDP/RDN pins directly.
3.4.7
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 0AH) is used to select
the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0] bits
(RCF0, 0AH) are used to select the AMI decoder or HDB3 decoder.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM1 and RXTXM0 pins.
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
RTIP
RRING
RTIP
RRING
normal receive mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
monitor
gain=0dB
TTIP
TRING
RTIP
RRING
normal transmit mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT82V2081PPG8 | 功能描述:IC LIU T1/J1/E1 1CH 44-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082_09 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082BFBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082BFG | 功能描述:IC LIU T1/E1/J1 2CH 81BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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