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參數(shù)資料
型號(hào): IDT82V2081PPG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 27/68頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 1CH 44-TQFP
標(biāo)準(zhǔn)包裝: 80
類型: 線路接口裝置(LIU)
規(guī)程: T1/E1/J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
其它名稱: 800-2347
82V2081PPG
IDT82V2081PPG-ND
33
INDUSTRIAL
TEMPERATURE RANGES
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.13 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2081 are indicated by the INT pin.
When the INT_PIN[0] bit (GCF, 02H) is ‘0’, the INT pin is open drain active
low, with a 10 K
external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 02H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
AnactivelevelontheINTpinrepresentsaninterruptoftheIDT82V2081.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 19H) or (INTS1, 1AH). Every kind of interrupt can
be enabled/disabled individually by the corresponding bit in the register
(INTM0, 14H) or (INTM1, 15H). Some event is reflected by the correspond-
ing bit in the Status Register (STAT0, 17H) or (STAT1, 18H), and the Inter-
rupt Trigger Edge Selection Register can be used to determine how the
Status Register sets the Interrupt Status Register.
AftertheInterruptStatusRegister(INTS0,19H)or(INTS1,1AH)isread,
the INT pin become inactive.
There are totally fourteen kinds of events that could be the interrupt
source:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13).Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-22 is a summary of all kinds of interrupt and the associated Status
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
3.14 5V TOLERANT I/O PINS
All digital input pins will tolerate 5.0 ± 10% volts and are compatible with
TTL logic.
3.15 RESET OPERATION
The chip can be reset in two ways:
Software Reset: Writing to the RST register (01H) will reset the chip
in 1 us.
Hardware Reset: Asserting the RST pin low for a minimum of 100
ns will reset the chip.
After reset, all drivers output are in high impedance state, all the internal
flip-flops are reset, and all the registers are initialized to default values.
3.16 POWER SUPPLY
This chip uses a single 3.3 V power supply.
Table-22 Interrupt Event
Interrupt Event
Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection bit
(INTES)
Interrupt Mask bit
(INTM0, INTM1)
LOS Detected
LOS_S
LOS_IS
LOS_IES
LOS_IM
AIS Detected
AIS_S
AIS_IS
AIS_IES
AIS_IM
Driver Failure Detected
DF_S
DF_IS
DF_IES
DF_IM
TCLK Loss
TCLK_LOS
TCLK_LOS_IS
TCLK_IES
TCLK_IM
Synchronization Status of PRBS/QRSS
PRBS_S
PRBS_IS
PRBS_IES
PRBS_IM
PRBS/QRSS Error
ERR_IS
ERR_IM
Code Violation Received
CV_IS
CV_IM
Excessive Zeros Received
EXZ_IS
EXZ_IM
JA FIFO Overflow
JAOV_IS
JAOV_IM
JA FIFO Underflow
JAUD_IS
JAUD_IM
Equalizer Out of Range
EQ_S
EQ_IS
EQ_IES
EQ_IM
Inband Loopback Activate Code Status
IBLBA_S
IBLBA_IS
IBLBA_IES
IBLBA_IM
Inband Loopback Deactivate Code Status
IBLBD_S
IBLBD_IS
IBLBD_IES
IBLBD_IM
One-Second Timer Expired
TMOV_IS
TIMER_IM
Error Counter Overflow
CNT_OV_IS
CNT_IM
Arbitrary Waveform Generator Overflow
DAC_OV_IS
DAC_OV_IM
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