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| 型號(hào)： | IDT82V2108BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 287/292頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 144-BGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2108BBG |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
84
March 5, 2009
3.19
JITTER ATTENUATOR (RJAT/TJAT)
The Jitter Attenuator of each framer operates independently
3.19.1
E1 MODE
Two Jitter Attenuators are provided independently in the receive
path and the transmit path.
The Jitter Attenuator integrates a FIFO and a DPLL. The smoothed
clock output from the jitter attenuator is generated by adaptively dividing
the 49.152MHz XCK according to the phase difference between the out-
put smoothed clock and the input reference clock. The ratio between the
frequency of the input reference clock and the frequency applied to the
phase discriminator input is equal to the (N1 + 1) (the N1 is in b7~0, E1-
021H for receive path and in b7~0, E1-025H for transmit path). The ratio
between the frequency of the output smoothed clock and the frequency
applied to the phase discriminator input is equal to the (N2 + 1) (the N2
is in b7~0, E1-022H for receive path and in b7~0, E1-026H for transmit
path). The phase fluctuations of the input reference clock are attenuated
by dividing the input reference clock and output smoothed clock by the
(N1 + 1) and the (N2 + 1) respectively in the DPLL so that the frequency
of the output smoothed clock is equal to the average frequency of the
input reference clock. The phase fluctuations with a jitter frequency
above 8.8 Hz are attenuated by 6 dB per octave when the N1 (b7~0, E1-
021H for receive path and b7~0, E1-025H for transmit path) and the N2
(b7~0, E1-022H for receive path and b7~0, E1-026H for transmit path)
are set to their default value. It will change when the N1 and the N2 are
changed. Generally, when the N1 and the N2 increase, the curves of the
Jitter Tolerance and Jitter Transfer in the graph will left-shift and when
N1 and N2 decrease, they will right-shift. The phase fluctuations (wan-
der) with frequency below 8.8 Hz are tracked by the output smoothed
clock. The output smoothed clock is used to clock the data out of the
FIFO.
The FIFO is 48 bits deep. If data is still written into the FIFO when
the FIFO is already full, overflow will occur and the OVRI (b1, E1-020H
for receive path and b1, E1-024H for transmit path) will indicate. If data
is still read from the FIFO when the FIFO is already empty, under-run will
occur and the UNDI (b0, E1-020H for receive path and b0, E1-024H for
transmit path) will indicate. Thus, if the OVRE (b2, E1-023H for receive
path and b2, E1-027H for transmit path) and the UNDE (b3, E1-023H for
receive path and b3, E1-027H for transmit path) are set respectively, the
interrupts on the INT pin will occur. The jitter attenuation can be limited
by setting the LIMIT (b0, E1-023H for receive path and b0, E1-027H for
transmit path) to keep the FIFO 1 UI away from being full or empty.
Thus, the DPLL will track the jitter of the input reference clock by
increasing or decreasing the frequency of the output smoothed clock to
prevent the FIFO being empty or full. The FIFO can also self-center its
read pointer by setting the CENT (b4, E1-023H for receive path and b4,
E1-027H for transmit path). The FIFO can be set to be bypassed by the
FIFOBYP (b7, E1-000H for receive path and b7, E1-002H for transmit
path).
However, in the Transmit Clock Master mode, the TJAT should be
bypassed.
3.19.1.1
Jitter Characteristics
Each Jitter Attenuator block provides excellent jitter tolerance and
jitter attenuation while generating minimal residual jitter. It can accom-
modate up to 43 UIpp of input jitter at jitter frequencies above 9 Hz. For
jitter frequencies below 9 Hz, which can be correctly called wander, the
tolerance increases 20 dB per decade. In most applications the each Jit-
ter Attenuator block will limit jitter tolerance at lower jitter frequencies
only. For high frequency jitter, above 10 kHz for example, other factors
such as clock and data recovery circuitry may limit jitter tolerance and
must be considered. For low frequency wander, below 10 Hz for exam-
ple, other factors such as slip buffer hysteresis may limit wander toler-
ance and must be considered. The Jitter Attenuator blocks meet the low
frequency jitter tolerance requirements ITU-T Recommendation G.823.
The Jitter Attenuator exhibits negligible jitter gain for jitter frequen-
cies below 9 Hz, and attenuates jitter at frequencies above 9 Hz by 20
dB per decade. In most applications the Jitter Attenuator blocks will
determine jitter attenuation for higher jitter frequencies only. Wander,
below 10 Hz for example, will essentially be passed unattenuated
through the Jitter Attenuator. Jitter, above 10 Hz for example, will be
attenuated as specified, however, outgoing jitter may be dominated by
the generated residual jitter in cases where incoming jitter is insignifi-
cant. This generated residual jitter is directly related to the use of 24X
(49.152 MHz) digital phase locked loop for transmit clock generation.
The Jitter Attenuator meets the jitter transfer requirements of ITU-T
Recommendations G.737, G.738, G.739, and G.742.
3.19.1.2
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter
frequency that a device can accept without exceeding its linear operat-
ing range, or corrupting data. For the Jitter Attenuator, the input jitter tol-
erance is 43 UIpp with no frequency offset. The frequency offset is the
difference between the frequency of XCK divided by 24 and that of the
input reference clock.
Refer to Figure 65 for the Jitter Tolerance.
3.19.1.3
Jitter Transfer
The output jitter for jitter frequencies from 0 to 9 Hz is no more than
0.1 dB greater than the input jitter. Jitter frequencies above 9 Hz are
attenuated at a level of 6 dB per octave, as shown in Figure 66.
3.19.1.4
Frequency Range
In the non-attenuating mode, that is, when the FIFO is within 1 UI of
overrunning or under running, the tracking range is 1.963 to 2.133 MHz.
The guaranteed linear operating range is 2.048 MHz ± 1278 Hz with no
jitter or XCK frequency offset.
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