參數(shù)資料
型號: IDT82V2608BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 數(shù)字傳輸電路
英文描述: INVERSE MULTIPLEXING FOR ATM
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA208
封裝: PLASTIC, BGA-208
文件頁數(shù): 24/98頁
文件大?。?/td> 398K
代理商: IDT82V2608BB
INTERFACE
24
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
3.3
EXTERNAL MICROPROCESSOR INTERFACE
The IDT82V2608 uses an embedded controller and a downloaded
software (IMAOS08 or IMAOS08_Slave
1
) to communicate with the
external mcroprocessor. The external mcroprocessor sends commands
to configure the device and read feedbacks. The downloaded software
interprets these commands and the embedded controller executes
these commands. This relieves programmers fromaccessing vast regis-
ters. Just by accessing a few registers, programmers can use a set of
well-defined commands to communicate with IDT82V2608.
3.3.1
EXTERNAL MICROPROCESSOR INTERFACE SELECTION
The IDT82V2608 supports both non-multiplexed Intel and non-multi-
plexed Motorola mcroprocessor interfaces. For Intel mcroprocessor
interface, the MPMpin should be connected to VDD; for Motorola mcro-
processor interface, the MPMpin should be connected to ground.
3.3.2
COMMAND FIFOS
The embedded controller uses two FIFOs to communicate with the
external mcroprocessor. One is Input FIFO, which is used to receive
commands and data fromthe external mcroprocessor; the other is
Output FIFO, which is used to send data to the external mcroprocessor.
The lengths of these two FIFOs are both 16 bytes. These two FIFOs can
only be accessed through registers.
3.3.3
REGISTERS
The IDT82V2608 provides 9 registers for the external mcropro-
cessor to load software to the device, send commands and read feed-
backs.
3.3.4
REGISTER MAP
1. IMAOS08 is used when the device is in normal communication while
IMAOS08_Slave is used when the device operates in Slave Mode. Refer to
8.1
Group Auto Detect
.
Table-4 Register Map
Address
(Hex)
Register
R/W
Map
b7
b6
b5
b4
b3
b2
b1
b0
00
INPUT_FIFO_LENGTH_REG
R/W
-
-
-
Input_Message_Length[4:0]
01
OUTPUT_FIFO_LENGTH_R
EG
R
-
-
-
Output_Message_Length[4:0]
02
OUTPUT_FIFO_DATA_REG
R
Output_Data[7:0]
03
INPUT_FIFO_DATA_REG
R/W
Input_Data[7:0]
04
FIFO_INT_ENABLE_REG
R/W
-
-
-
-
-
Input_FIFO_
empty_int_en
Input_FIFO_ov
erflow_int_en
Output_FIFO_msg
_available_int_en
05
FIFO_STATE_REG
R
HW_version
Input_FIFO_
empty_state
Input_FIFO_ov
erflow_state
Output_FIFO_msg
_available_state
06
FIFO_INT_RESET_REG
W
-
-
-
-
-
-
Input_FIFO_ov
erflow&empty_i
nt_rst
Output_FIFO_msg
_available_int_rst
07
OUTPUT_FIFO_INTERNAL_
STATE_REG
R
-
-
-
Output_remain_msg_length[4:0]
08
INPUT_FIFO_INTERNAL_ST
ATE_REG
R
-
-
-
Input_remain_msg_length[4:0]
相關PDF資料
PDF描述
IDT82V2608 INVERSE MULTIPLEXING FOR ATM
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
IDT82V3001APV WAN PLL WITH SINGLE REFERENCE INPUT
IDT82V3002A WAN PLL WITH DUAL REFERENCE INPUTS
IDT82V3002APV WAN PLL WITH DUAL REFERENCE INPUTS
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