參數(shù)資料
型號(hào): IDT82V3001A
廠商: Integrated Device Technology, Inc.
英文描述: WAN PLL WITH SINGLE REFERENCE INPUT
中文描述: 廣域網(wǎng)鎖相環(huán)單參考輸入
文件頁(yè)數(shù): 13/27頁(yè)
文件大?。?/td> 345K
代理商: IDT82V3001A
13
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
Figure - 6 State Switch with TIE Control Block Enabled
The phase difference in the Storage Circuit can be cleared by
applying a logic low pulse to the
TCLR
pin. The reset pulse should be at
least 300 ns.
When the IDT82V3001A primarily enters Holdover Mode for short
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
phase change between the input and output.
If the TIE Control Block is disabled manually or automatically during
state switching, the phase of the output signal will align with that of the
new reference. The phase slope limited to 5 ns per 125 μs.
Figure - 7
shows the phase transient resulting from a state switch with the TIE
Control Block disabled.
Figure - 7 State Switch with TIE Control Block Disabled
3.5
DPLL BLOCK
As shown in
Figure - 8
, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers.
Input Clock
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
Input Clock
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
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